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TChin5
Beginner
1,394 Views

Still cannot assign LVDS signal to MAX-V device

I try your suggestion. I have a single-ended signal call OUT_P and assigned it as LVDS_E_3R, the pin planner created the corresponding diff signal call OUT_P(P).

When I compile it, Quartus returns a pop-up problem report window.

The short version of the Preview of the report :

 

Problem Details

Error:

Internal Error: Sub-system: FYGR, File: /quartus/fitter/fygr/fygr_cdr_op_place.cpp, Line: 1882gid != DEV_ILLEGAL_GLOBAL_IDFitter pre-processing

Stack Trace: ....................................

................................

Executable: quartus_fit

Comment:

None

 

System Information

Platform: windows64

OS name: Windows 10

OS version: 10.0

 

Quartus Prime Information

Address bits: 64

Version: 17.1.0

Build: 590

Edition: Lite Edition

0 Kudos
14 Replies
Abe
Valued Contributor II
252 Views

Can you archive your project and post it here.. let us check it out.. Maybe you can also download the latest 18.1 version and try in the meantime.

TChin5
Beginner
252 Views

Attached is the archive file. I have to change the file extension to text otherwise I can't upload it. (the Answer button gets gray out when it is of type ".RPT")

I have already tried Quartus 18.1 with no luck.

I choose LVDS_E_3R because MaxV only support this.

The file was able to compile when I change only this pin to another I/O standard but fail when I change it back

Abe
Valued Contributor II
252 Views

This is the archive report file and is useless for me. Please upload the .QAR file. I can then check what the issue is about. You can upload the QAR file in this forum and I've done it earlier.

TChin5
Beginner
252 Views

see attached, Is this the right file you need

Abe
Valued Contributor II
252 Views

I've looked into the project and resolved the LVDS issue. I've deleted the ALTLVDS_TX IP as it is not needed, but haven't removed the other IP components. If you are not using these, please do remove them.

 

Another point to be noted is that I've used v18.0 lite and created this QAR file, so I would suggest you open this file with v18.1 and upgrade the IP components. Then do a PRoject Clean and then Compile. It should work this time. The LVDS assignments are OUT_P(p) -> PIN_D15 and OUT_P(n) gets assigned to PIN_C14. It compiles fine without the errors.

TChin5
Beginner
252 Views

But I never use the ALTLVDS_TX IP in my design. I only have it there because my LVDS signal was causing compile issue and was trying out this part, it didn't help and I have commented them out as seen at the bottom of my file. I try this design in using V18.1 lite and it didn't work.

Attached is the 18.1 archive.

 

I un-archive your design and it compile but What did you do to the designed to get it to work

TChin5
Beginner
252 Views

The only different I noticed is that my pin planner assigned OUT_P(N) to C14 and yours is empty.

 

I try duplicating it by deleting OUT_P(N) but this also remove OUT_P(P), therefore I can't seem to it.

SInce Mine still didn't work with v18.1 lite, ........What did you do to get it to work

 

TChin5
Beginner
252 Views

I try to edit the archive with the pin planner that you returned to match the pinout with my design for OUT_P(N) to C14 at the column "Location" but Quartus said "Editing location assignment is not successful. The differential pair pin is assigned" I won't allow me to edit this field. even thought the column "Filter Location" said PIN C14.

I thought these two column (Location and Fitter Location) are the same.

Your Archive has this field (Location) empty but mine have this field set to C14.

I'm confused,.

 

TChin5
Beginner
252 Views

attach is the different between mine and yours.

I fact when I try to put c14 into your archive, the tool crash

TChin5
Beginner
252 Views

OK, I have recreated the problem that I have but I 'm still dont know how to fit it.

I took the archive that you send to me. It compile OK.

 

Now I change the the signal "OUT_P" to cmos and IOBank to 3.3v and that compile

Next I change it back to lvds and IOBank to 2.5v, now pin planner creates the other diff signal and assigned C14 to it.

Now it crash just like before.

 

I cannot get it back to the state that you sand me where the Location field for OUT_P(N) is empty.

It is when this field is empty then it compile.

 

How did you get this field to be empty

 

 

Abe
Valued Contributor II
252 Views

Hi,

 

Sorry, it was past my bedtime earlier. Well, here's what I did to resolve the issue:

 

  1. Remove the ALTLVDS IP.
  2. Clean the Project
  3. Remove the C14 OUT_P(n) assignment since the tool will assign this automatically. (Assignment Editor)
  4. Made sure the IO Standards are correct. Bank 2 in your project is configured for 2.5V, the OUT_P signals cannot be assigned to 3.3V LVCMOS/LVTTL standards. This should be 2.5V only.
  5. Assign only the OUT_P signal to PIN_D15 and compile the design. The Tool automatically assigns PIN_C14 for the OUT_P(n) signal (Emulated LVDS pair) and compiles the design.
  6. Used Pin Planner tool and not Assignment editor to make the assignments.

 

Point to be noted -

When assigning / working with LVDS , the core logic will always be single-ended. We assign only the +ve PIN of the device to the output signal and set the IO Standard as LVDS and match the IO Voltage to the one the Bank is using.

The -ve (pair) signal need not be assigned manually in the Pin Planner or Assignment editor. Assigning this will cause the tool to generate errors and the compilation to fail. This is coz the tool generates and assigns the LVDS pair automatically.

 

Hope this clears your doubts. You need not generate the +ve and -ve LVDS signals in your VHDL code. Just use the single-ended logic like always. Assign the LVDS output signal to the (p) Pin in Pin Planner/Assignment editor, set IO standard to LVDS and compile. The tool will do the rest.

 

I've modified the v18.1 project file you sent and tested it. It compiles fine. You can check it out.

TChin5
Beginner
252 Views

Hi,

 

According to your reply in step 6, I did use pin planner to assign my lvds. Once I assigned "OUT_P" with IOStandard=LVDS and Location=D15.

Pin Planner automatically assigned C14 to OUT_P(N).

I didn't touch this other diff signal, Pin planner assign it. If you look at my design with Pin planner, yours has an empty location field there but mine has it populated with C14. see attachment

This cause my compilation to fail and your to pass

 

I did try to compile the design you send back and it pass but I cannot duplicate it on mine side.

I cannot get that empty location field to show up.

Even after I delete it and reassigned it to the positive-end, pin planner always assign the negative-end and fill that location field

cossy
Beginner
187 Views

Hi TChin5:

I have tried the proj, in the end i find one thing:

when you assign the LVDS pin, the .qsf maybe like below:

"
line 1: set_instance_assignment -name IO_STANDARD LVDS_E_3R -to send_data

line 2: set_location_assignment PIN_78 -to send_data
line 3: set_instance_assignment -name IO_STANDARD LVDS_E_3R -to "send_data(n)"
line 4: set_location_assignment PIN_77 -to "send_data(n)"
line 5: set_global_assignment -name SLD_FILE db/stp1_auto_stripped.stp

"

 

you should del the line 3 and line 4 manually , and compile it , then you will see the send_data(n) pin assignment is null, and it can be done.

I haven`t test the real LVDS signal recently .  will try later

 

BR

Seiya

 

 

cossy
Beginner
186 Views

Hi TChin5:

I have tried the proj, in the end i find one thing:

when you assign the LVDS pin, the .qsf maybe like below:

"
line 1: set_instance_assignment -name IO_STANDARD LVDS_E_3R -to send_data

line 2: set_location_assignment PIN_78 -to send_data
line 3: set_instance_assignment -name IO_STANDARD LVDS_E_3R -to "send_data(n)"
line 4: set_location_assignment PIN_77 -to "send_data(n)"
line 5: set_global_assignment -name SLD_FILE db/stp1_auto_stripped.stp

"

 

you should del the line 3 and line 4 manually , and compile it , then you will see the send_data(n) pin assignment is null, and it can be done.

I haven`t test the real LVDS signal recently .  will try later

 

BR

 

 

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