Strange - counter counts without clock

[Altera_Forum]

Something strange happened, and I have no idea for now, what to look for... Below you can see the part of the schematics (testing on DE2-115 board, clk frequency - 10MHz). Very straightforward design, nothing interesting or complicated. 

 And it was working just fine until recently – suddenly the counter A started behaving in unexplained (at least, for me) way. Instead of switching just once on each clock (signal 111) now it switches extra time without any visible reason. On second picture you can see the actual signals from 111 (red) and 41 (blue).  Another thing – sometimes if I make changes in other parts of the schematics (not related to this part at all), it starts working normal again.  I would very appreciate if someone can point me in proper direction…

[Altera_Forum]

looks like you are connecting outputs of counter as feedback to clock the counter. This is complicated design and may oscillate out of control. 

Your method falls in the category of asynchronous which is not recommended in FPGAs as the alternative synchronous design is simpler to control.

[Altera_Forum]

I know the design is not the best, but in this particular case I don't see anything that can cause such behavior. The oscilloscope does not show anything.  

 Of course, the glitch can be just too short for my equipment...

[Altera_Forum]

When an internal node is connected to a pin, it does not necessarily take the same internal node. 

In this case, 111 that feeds to CLKA may not be the same node that is connected out for observation. You can imagine that there are 2 sets of NAND, NOR and INV internally. Timings are slightly different. There can be glitch driving to CLKA but not the one connected to oscilloscope.

[Altera_Forum]

As a first step, look at the gate level netlist (Technology Map Viewer) to understand how the logic is actually implemented. 

 You'll notice that the 7493 3-bit block (QB..QD) is synthesized as a synchronous counter, in contrast to the original 7493 ripple counter. The combinational logic is implemented in a single logic cell.   The glitch occurs at a time when all three counter flip-flops change state. If more than one input of a LUT (logic element) changes state simultaneously, output glitches can occur. If it really happens depends on arbitary routing and LE internal delays. See http://www.alteraforum.com/forum/showthread.php?t=26151 or similar previous threads.   That's why the shown design style must be considered unsafe.

[Altera_Forum]

Thanks to everyone who found time to reply !

[Altera_Forum]

--- Quote Start ---  When an internal node is connected to a pin, it does not necessarily take the same internal node. In this case, 111 that feeds to CLKA may not be the same node that is connected out for observation. You can imagine that there are 2 sets of NAND, NOR and INV internally. Timings are slightly different. There can be glitch driving to CLKA but not the one connected to oscilloscope.  --- Quote End ---    By the way, the question - does SignalTap show real signals ?

[Altera_Forum]

Signaltap shows whatever you connect to it at the specified sample frequency.