Re: Strange, counter forgets to count

Altera_Forum · ‎04-08-2014

Why is that sometimes, a register forgets to increment? Any causes for this? (at the attached picture, it the 'addr' should count up, but it didn't). Does a 100Mhz clock have something to do with it? Its strange

https://www.alteraforum.com/forum/attachment.php?attachmentid=8716

Altera_Forum · ‎04-08-2014

Because some conditions occured that meant it didnt count?

Or is your sample clock different from the clock that clocks addr?

Altera_Forum · ‎04-08-2014

--- Quote Start ---

Because some conditions occured that meant it didnt count?

Or is your sample clock different from the clock that clocks addr?

--- Quote End ---

I double check the signal tap data, and the condition is there.. its just that the 'addr' forgot to change.. :(


initial
begin
	address <= 0;
	chipselect <= 1'b1;
	byteenable <= 2'b00;
	reset <= 1'b1;
	read <= 1'b1;
	write <= 1'b1;
	state <= wzero;
	writedata <= 0;
end
parameter rzero=4'b0000, rone=4'b0001, rtwo=4'b0010, rthree=4'b0011, rfour=4'b0100, rfive=4'b0101;
parameter wzero=4'b1000, wone=4'b1001, wtwo=4'b1010, wthree=4'b1011, wfour=4'b1100, wfive=4'b1101, woneone=4'b1110;
always @(posedge ramclk)
begin
case (state)
wzero:
			begin
				address <= address + 0;
				if(address == 999999)
					lastread <= writedata;
				if(address == 1000000)
					state <= rzero;
				else if(pclk)
					begin
						state <= wone;
						write <= 1;
						address <= address + 1'b1;
						writedata <= writedata + 1;
					end
				else
						state <= wzero;
			end
		wone:
			begin
			address <= address + 0;
				state <= wtwo;
				write <= 0;
			end
		wtwo:
			begin
			address <= address + 0;
				if(pclk)
					begin
						state <= wthree;
						write <= 1;
					end
				if(!pclk)
					begin
						state <= wzero;
						write <= 1;
					end
			end
		wthree:
			begin
			address <= address + 0;
				if(!pclk)
					begin
						state <= wzero;
					end
				else
						state <= wzero;
			end
		rzero:
			begin
				read <= 0;
				address <= 999999;
				state <= rone;
			end
		rone:
			begin
				read <= 1;
				state <= rone;
			end
			default:
			state <= wzero;
	endcase
end