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Valued Contributor III
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Strange effects with NIOS in design

Hi everyone, 

 

For the first time I am using a NIOS soft core in one of my designs. Generating the core was relatively easy but now I'm facing some strange effects when I integrate the core into my design. 

 

In my design, I'm using four bidirectional pins for two separate I2C buses. Without the NIOS in the design everything works fine and I'm able to communicate with the devices on I2C bus, but as soon as I add the core to the design, two out of four I2C pins are not usable anymore. They remain on high state even if I try to drive them low. So far, the NIOS was only added to the design, it was not yet connected to one of these I2C pins. 

Does anyone have an idea what could cause this problem and how to resolve it?
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Valued Contributor III
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Are you using an I2C IP to control the interfaces? What is the Nios connected to? What do your pin assignments look like? What device are you using? Quartus version? I think more details are required here.

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Valued Contributor III
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Ok, let me give you some more details: 

I'm using a Cyclone V: 5CGXBC4C7F27C8 and work with Quartus Prime version 17.0 Standard Edition. The Nios consists of the cpu (Nios II/e), the cpu_memory, six PIO output ports and three PIO input ports. The I2C master is located outside the Nios, directly in the design where the Nios should be used. So far I did not connect the Nios to the rest of the design for testing (which means that the Nios is not yet connected to any I2C master so far). There is also no I2C master in the design yet, the two pins which I want to use for I2C communication are driven low by using: I2C_SCL_NA_MID <= '0'; and I2C_SDA_NA_MID <= '0';. 

The I2C pins are configured for bidirectional use. The pin assignments are the following: 

set_location_assignment PIN_AB22 -to I2C_SCL_NA_MID 

set_location_assignment PIN_AC23 -to I2C_SDA_NA_MID 

set_instance_assignment -name AUTO_OPEN_DRAIN_PINS ON -to I2C_SCL_NA_MID 

set_instance_assignment -name AUTO_OPEN_DRAIN_PINS ON -to I2C_SDA_NA_MID 

If I use other pins than PIN_AB22 and PIN_AC23 it works well. And also if I remove the Nios from the design, I'm able to drive these two pins low again. It is only not working if I add the Nios to the design. Is it possible that the Nios takes control of these two pins (or also other pins)?
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Valued Contributor III
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I don't have an answer for you, but you can see pinout details for your device here: https://www.altera.com/support/literature/lit-dp.html 

 

AC23 is listed as having the partial reconfiguration request signal as a configuration function, but I doubt that has anything to do with your issue (unless for some reason you've enabled the external PR pins in the Device settings). 

 

Have you checked the compilation report for these pins? Perhaps there is a message in there somewhere that might explain what's going on.
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Valued Contributor III
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Thanks for you answer sstrel. I did check the pinout details for my FPGA, but couldn't find anything what could cause my issue. I did also check the compilation report several times, but the only thing I found was the following: 

 

Info (169065): Pin I2C_SCL_NA_MID has a permanently enabled output enable 

Info (169065): Pin I2C_SDA_NA_MID has a permanently enabled output enable 

 

I don't think that this is my problem. Still, I think it has to do something with the NIOS. As soon as I remove the NIOS from the design, everything works fine. When looking at the Technology Map Viewer, it shows me that the output pins should be driven to GND (see attached picture).  

 

https://www.alteraforum.com/forum/attachment.php?attachmentid=14189  

 

Also the follwing message in the compilation report tells me that this pins should be driven to GND: 

 

Warning (13032): The following tri-state nodes are fed by constants 

Warning (13033): The pin "I2C_AUTH_SCL" is fed by GND 

Warning (13033): The pin "I2C_AUTH_SDA" is fed by GND 

Warning (13033): The pin "I2C_SCL_NA_MID" is fed by GND 

Warning (13033): The pin "I2C_SDA_NA_MID" is fed by GND 

 

So if the compilation report tells me that the pins should be driven by GND and also the Technology Map Viewer shows me a pin which should be driven by GND, it lets me assume that the NIOS has the possibilty to interact directly with the pins and somehow overdrives the pin function. Is this possible? And if so, where could this be configured in the NIOS?
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