Strange problem : Edge capture in a State Machine seems not beeing captured

Altera_Forum · ‎07-23-2009

Hi,

In a State machine, falling edge capture of a signal seems not working

or state machine has a mistake.


    block_reception : block
    begin
        process_reception : process (clk, reset_n)
            variable detect : std_ulogic_vector(1 downto 0) ; 
            variable cnt : integer range 0 to 5;
        begin
            if reset_n = '0' then
                cnt := 0;
            
                state <= Repos;
                
                ld_rx <= '0';
                sclr_rx <= '0';
                rx_available <= '0';                
                erreur <= '0';                
                pulse <= '0';
               
            elsif rising_edge(clk) then
                detect(1) := detect(0); -- edge capture detection
                detect(0) := clk_iso2;
                -- par défaut
                ld_rx <= '0';
                sclr_rx <= '0';
                rx_available <= '0';
                erreur <= '0';                
                pulse <= '0';
 
                case state is
               
                    -- Repos
                    when Repos=>
                       ...                       
                    
                    when st_wait_ss=>
                        cnt := 0;
                        state <= st_wait_ss;
                        
                        if raz_iso2 = '1' then
                            state <= Repos;
                        elsif code = '1' then 
                            state <= Repos;
                        elsif detect = "10" then -- falling edge
                            ld_rx <= '1';                                
                            ...
                            
                        else
                            state <= st_wait_ss;
                        end if;
                       
                    when st_stock_data=>
                        state <= st_stock_data;
                        if raz_iso2 = '1' then
                          state <= Repos;
                        elsif detect = "10" then -----------------------mistake here, i think----------
                            ld_rx <= '1';
                            
                            cnt := cnt + 1;
                            if cnt > 4 then -- enregistrement tous les 5 fd clk_iso2
                                cnt := 0;
                                ...                                
                            end if;
                            
                        elsif code = '1' then
                            state <= Repos;
                        else
                            state <= st_stock_data;
                        end if;
                    
                    when others => null;
                end case;
            end if;
        end process;
    end block;

I use SignalTap to look for signals and I see that counter cnt stops counting or goes back to 0 not at the good moments.

ld_rx signal is strange too.

So, where it is wrong ?

it is like if some falling_edge of clk_iso2 are not captured.

Altera_Forum · ‎07-24-2009

Is signal "clk_iso2" an actual clock, on a clock net? is it used for clocking logic?

Basically I can see two problems here:

1. If "clk_iso2" is actually a clock, then I would NOT recommend sampleing it at all. Use some other logic instead.

2. Is "clk_iso2" in the same clock domain as "clk"? if it is not, you will need to sample it via two registers to prevent meta-stability. I assume that it isnt in the same clock domain as "clk" as you're having problems, so sampling it is going to throw up all sorts of problems. Also, "clk" must be running faster than "clk_iso2" for you to be able to capture any meaningful changes in it.

Altera_Forum · ‎07-27-2009

Thanks for answer,

For information,

clk_iso2 : I have to strobe data on falling edges of clk_iso2. It is NOT a clock. It is like a strobe. Freq about 150kHz

It was a stupid graphical problem in bdf file that causes the metastability problem : I forgot renaming some signals.

[resolved]