Stratix 10 Configuration Issue

[Balasubramani]

Hi,

We are facing a issue while configuring Stratix10 FPGA ( Smart VID variant) from JTAG Port

We have a fixed failure, failing at 9% always while loading sof file. The same architecture is being used in other chain on the same card with all conditions same and there configuration is working fine

All power rails good and stable, JTAG path is good

PMBUS Alert# is going low while configuring

Kindly suggest any debugging tips

[WZ2]

Hi there,

Do we have the pic of quartus error ID~ It may helpful me.

Best regards,

WZ

[Balasubramani]

Hi,

I have attached the pictures for error messages with error ID

We have total 2 identical cards with 2 Stratrix10 FPGAs on each card ( RX & TX Chain). The same configuration file is working on one card and not on the other and vice-versa

[WZ2]

Hi there,

It seems like SmartVid error. In a word, the device cannot communicate with voltage regulator by PMBUS/ There is some advice:

1. Check the line of pmbus_clk pmbus_data between device(SDM) to voltage regulator
2. check the PMBUS setting in quartus: Assignment->Device->device and pin opinion->Power management&VID. These setting should be based on the datasheet of voltage regulator.

More information can refer this link:

https://www.intel.com/content/www/us/en/docs/programmable/757318/current/and-smartvid-debug-checklist-and-voltage.html

Best regards,

WZ

[Balasubramani]

Hi, 

We have set the SmartVID settings as recommended, but unable to calculate 'Linear format N' value for LTM4680 power module for output voltage of 0.85V. We have tried both the cases by setting Voltage output format to 'Auto discovery' and 'Linear format' with N value as -12, -14, -15, but programming was unsuccessful

Please tell us how to get the N value

[WZ2]

Hi there,

Sorry for the delay due to public holidays.

Normally, the PMBUS parameters should be provided by the Voltage regulator manufacturer (AD). Except for N, the slave address should also be changed according to your circuit design (LTM4680 characteristics).

Best regards,

WZ

[WZ2]

I read the datasheet, I think N=-12 should be worked, please check the slave address~

[Balasubramani]

Hi,

Thank you sharing the information

We have set the N value to be -12 and set different slave address ( 0x4F, 0x47), but didn't work, we get the same reply as "Incorrect VID Settings"

Kindly let me know if it could be due to Quartus Prime version

[moglesb1]

It sounds like there are 2 identical boards, one works, one does not.

Based on the above, will assume that you have the correct QSF settings in regards to MODE and Exponent.

The LTM4680 is a dual channel/output device, if you are using both channels to create a single 60A rail, you need to make sure the PAGE command is set to 0xFF.

Older versions of Quartus only have a single "Enable PAGE command" enable/disable box and default to a PAGE of 0xFF.

Newer versions of Quartus have an additional "Page value" dialog.

If using both channels, this gets set to 0xFF

If only using one of the channels, ensure the PAGE matches the channel you are driving (0x00, 0x01)

The LTM4680 is very close to the LTM4677 in regards to the controller so you could choose that in the Quartus Drop Down.

This has the benefit of speeding the VR's internal ADC's voltage reading by issuing the "MFR_ADC_CONTROL" , it can help with configuration speeds. 

The Voltage reporting can be in VOLTS or MILLIVOLTS.  Linear VR's typically report their voltage in VOLTS so make sure to select that in the Quartus drop down "Translated voltage value unit". 

The address of this device can be set using strapping resistors or overridden via NVM settings inside of the VR. 

The things to check, look at the PMBus on both sides of your level-shifter, ensure they are pulled-up with no traffic is flowing. Ensure the Level-Shifter is enabled, allowing traffic to flow between the S10 and the VR.

Check out the PMBus commands being sent on both sides of the level shifter.  Ensure the signals have nice edges and are not sloped.  Depending on your design and the level shifter that was used, capacitance from the 3.3V side of the level shifter can load the 1.8V side.  If you see the edges are not clean, try increasing the strength of the pull-ups. 

You mentioned that the ALERT signal was being asserted.  Assuming this is the ALERT signal coming from the VR and not from the FPGA which only uses ALERT in Slave Mode.

If the VR is asserting ALERT, then connect the LT Power Play application to the VR, it will let you inspect the fault.  Note, don't have the LT power Play dongle attached at the same time you are trying to run a config, it will cause contention. 

There are safety limits that need to be configured inside of the VR, this is done using the LT Power Play and USB Dongle.  You need to ensure the safety limits are configured to allow the entire voltage range needed by the FPGA.

The critical safety limits are:

  VOUT_OV_FAULT_LIMIT

  VOUT_OV_WARN_LIMIT

  VOUT_UV_WARN_LIMIT

  VOUT_UV_FAULT_LIMIT

  VOUT_MAX

During manufacture, each S10 FPGA has it's unique voltage requirement characterized.  This value gets saved inside each FPGA and is used by the FPGA's power management FW to set the VCORE voltage.  Each FPGA will have a unique Voltage requirement so its important that the VR is able to supply that value.