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Synthesis results and different behavior

Yamada1
Beginner
1,914 Views

I made an SPI interface circuit, but the SCLK output is always 'H' and it doesn't work.

It would be helpful if you could give me some hint to solve it.

The survey results are as follows.

  1) MOSI and NCS are output normally.

  2) Circuits are generated in Technology Map Viewer.

  3) It becomes 'H' immediately after configuration is completed, and does not become 'L' even if a reset signal is input.

 

I will attach the source of the relevant part and the image of Technology Map Viewer, so it would be helpful if you could give me some hints.

In addition, there is "SCLR" in the FF of s_sclk in image1.png, but is it correct to understand that when this is asserted, it synchronizes with CLK and Q = 'L'?

Sorry for the inconvenience, but thank you in advance.

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sstrell
Honored Contributor III
1,859 Views

1) Yes.  There are many VHDL attributes like this.  Just googled this: https://redirect.cs.umbc.edu/portal/help/VHDL/attribute.html

2) Not sure what you mean here, but if your clock is not coded correctly, then nothing is going to work correctly because it will never get to the if checks.

3) rising_edge is part of std_logic, so as long as you're using that library, it will work and is recommended.

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sstrell
Honored Contributor III
1,890 Views

Right off the bat from your code, you have your clock if-checks in all processes to "SYS_CLK' event" when it should be "SYS_CLK'event" (no space).  Better would be to use rising_edge(SYS_CLK).  This could be your whole problem because you would never get to the DATA_SHIFT_FLAG check for s_sclk to go low.

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Yamada1
Beginner
1,876 Views

Thank you for answering.

Thank you for pointing out about the synchronization circuit.

Sorry to trouble you, but it would be helpful if you could teach us the following points.

  1) Is "CLK'event" (without spaces) a rule of VHDL grammar? Or is it because it affects interpretation during synthesis of Quartus Prime?

  2) According to your answer, the reason is that the processing from line 157 onwards is not performed because the rise of CLK has not occurred. It seems that it is not working itself, but is that recognition correct?    3) In your answer, the description of "rising_edge(SYS_CLK)" is recommended, but is it possible in VHDL1993?

 

Sorry for the inconvenience, but thank you in advance.

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sstrell
Honored Contributor III
1,860 Views

1) Yes.  There are many VHDL attributes like this.  Just googled this: https://redirect.cs.umbc.edu/portal/help/VHDL/attribute.html

2) Not sure what you mean here, but if your clock is not coded correctly, then nothing is going to work correctly because it will never get to the if checks.

3) rising_edge is part of std_logic, so as long as you're using that library, it will work and is recommended.

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Yamada1
Beginner
1,847 Views

Thank you for answering.

I understand that "CLK'event" (no spaces) is the way to specify attributes.

As you pointed out, I confirmed the operation by synthesizing with the space removed from "SYS_CLK' event" on line 156 and synthesizing with "rising_edge (SYS_CLK)" changed, but there is no improvement It didn't (changed only parts that weren't working correctly to see the difference).

Will lines 152 to 165 not work properly due to other "SYS_CLK' events" (with spaces) in PLL_SPI.vhd?

 

I'm sorry to trouble you, but it would be helpful if you could teach me.

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sstrell
Honored Contributor III
1,834 Views

Fix the clock everywhere and then try it out to see if it works.  If it doesn't, reply back with what is still not working.  You should also include warning messages you get which can help clue you in to the issues in your design.

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Yamada1
Beginner
1,585 Views

Thank you for your comment.

As a result of correcting all sources, it was confirmed that it works normally.

Thank you very much for your detailed answer.

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RichardTanSY_Intel
1,820 Views

Do you able to get the expected result by changing to the rising_edge (SYS_CLK) ?


Best Regards,

Richard Tan


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Yamada1
Beginner
1,792 Views

Thank you for your comment.

Even if I changed it to "rising_edge (SYS_CLK)", it did not improve.

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RichardTanSY_Intel
1,681 Views

The code can be compiled correctly. However, I recommend reviewing your design in the RTL viewer to ensure that it has the desired functionality.


Could you please share your testbench and the simulation result with me? I would like to understand what is meant by "[SCLK output is always 'H']."


Best Regards,

Richard Tan


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RichardTanSY_Intel
1,650 Views

Hi,


Could you please share your testbench and the simulation result with me?

Please kindly indicate any issues or errors that occur in the simulation result.


Best Regards,

Richard Tan


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RichardTanSY_Intel
1,606 Views

We noticed that we haven't received a response from you regarding the latest previous question/reply/answer, and will now transitioning your inquiry to our community support. we are now transitioning your inquiry to our community support. We apologize for any inconvenience this may cause and we appreciate your understanding. If you have any further questions or concerns, please don't hesitate to let us know. Thank you for reaching out to us!


Best Regards,

Richard Tan


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