Stratix 10 H-tile PLL performance

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

Stratix 10 H-tile PLL performance

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I am looking for the PLL performance of H-tile transceiver for Stratix 10 GX device, I know ATX-PLL provides the best performance, but is there any detail parameter such as jitter when used to generate high-speed Tx clock and jitter tolerance when used in CDR mode in Rx to extract clock from received signal? I am targeting 25Gb/s application but it would be good to have parameters for different speeds.

Many Thanks

Chen

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