We have had problems with the stratix DSP kits (not Stratix II) what concerns Stratix configuration after power up. It seems not to be reliable, one in about 10 power-on cycles does not configure the Stratix FPGA.
Attached please find our own rewrite of the configuration controller code. It has been tested and found to work better and configures faster than the original version. During tests not one single failure to configure the FPGA has been seen.
The source code is supplied as opposed to the Altera version, so you can modify this to your pleasing. Be warned, though that the chip is almost full so fitting is an issue. You will find that changing one single bit may result in failure to fit, but fortunately it compiles quickly, so trial and error has worked in my case.
Quartus reports timing violations. But my guess is that it is the constraints which are not correctly set up to reflect the clock divider (x1/2) in the clock input. This divider is needed because the state machine can not operate at 80MHz as required.
Altera has restore kits for both the MAX7064 in question here as well as the safe-boot sector of the flash.
Please let me know how it works for you, but...
As usual NO WARRENTY. Use at you own risk.
