Stratix II Remote update without NIOS

[Altera_Forum]

All remote update examples and designs seem to use the NIOS as a wrapper for all this. I don't want to insert a NIOS into the design for this sole purpose. 

 My idea was to always have a factory image that boots, if there is a valid application image, then reconfigure from this image instead. Is that a common approach?  To update the image, I must myself write it to the EPCS16? How can the altremote megafunction know if it is correct? It doesn't have any ports to the memory?! Is it checked before loading?  Is there an application note or a finished design that implements remote update in Active Serial mode without a NIOS wrapper??  Very thankful for any help!  EDIT: I was also wondering about the physical layout. Is it possible to support JTAG configuration and active serial configuration in the same design? What should my layout be? Currently it looks like this: http://hygren.nu/fpga.gif

[Altera_Forum]

BUMP 

No one that can help? :'(

[Altera_Forum]

Please be patient, you asked your question during the holidays, and not everyone read the forum during new year's eve ;) 

I'm not aware of any remote update example without a CPU. In my opinion checking if a valid application image is present in the flash and reconfigure the FPGA from that is easier to do with a CPU than with just HDL.  You can support both JTAG and active serial configuration in the same design. The FPGA will load its configuration from the flash first, but you can also upload your image through JTAG. You can also access the flash memory from the JTAG interface by using a SFL (Serial Flash Loader).

[Altera_Forum]

Thanks for your reply! 

  --- Quote Start ---  You can also access the flash memory from the JTAG interface by using a SFL (Serial Flash Loader).  --- Quote End ---  That's the megafunction right? I will look into that.   What's your opinion on my layout? (http://hygren.nu/fpga.gif)  What needs to be done to check if there is a valid application image? Isn't checking the CRC enough?

[Altera_Forum]

Yes it is the megafunction. There is also a ready made sof file that contains only the SFL, that you can directly program into the FPGA. 

The layout seems fine, but are you sure that the MSEL pin should be connected to 3.3V? I don't know about the Stratix II (never used it) but I know that on the Cyclone III you must use a 2.5V (the PLL analog supply). Checking the CRC should be enough. You'll probably need to write a state machine that can instruct the EPCS to jump to the correct address, and then read the data to check the CRC.

[Altera_Forum]

I went through the Stratix datasheet and in fact you were right about the voltage. Contrary to the Cyclone III the Stratix uses the bank supply voltage for the MSEL pins. From what I saw, you would also need to connect MSEL0 to 1 to enable the remote update circuitry.

[Altera_Forum]

Thanks a bunch Daixiwen! I seem to have everything in order now, will produce the prototype board soon and verify the behavior.