Stratix II VCCSEL connection

[Altera_Forum]

How should I time VCCSEL of my Stratix II if VCCIO of Bank 3 is 1.8V and the configuration voltage requirements are 3.3V?

[Altera_Forum]

If the VCCIO of I/O bank 3 is powered by 1.5 or 1.8-V and the configuration signals used require 3.3- or 2.5-V signaling, you should connect VCCSEL to VCCPD in order to enable the 1.8V/1.5V input buffers for configuration. The 1.8-V/ 1.5-V input buffers are 3.3-V tolerant. This will also enable the FPGA to exit POR under these conditions.

[Altera_Forum]

Surfsup is correct. For more information refer to the Altera web site. Altera has published 3 known issues solutions to deal with this problem. Note that the affected text and table discussed in solutions rd03122007_78 and rd10112006_949 was originally written for PS and FPP mode but the documentation failed to clarify as such. In PS mode and FPP mode the lower trip point is selected by default independent upon VCCSEL pin setting. Altera is actively working to correct the handbook to minimize the impact to customers. 

 

• http://www.altera.com/support/kdb/solutions/rd06172005_556.html 
• http://www.altera.com/support/kdb/solutions/rd03122007_78.html 
• http://www.altera.com/support/kdb/solutions/rd10112006_949.html