Stratix IIGX question of comprehension

[Altera_Forum]

Hey all, 

I'm working with a PCIe development board that's equipped with (among other things) a Stratix II GX FPGA and 2 SFP channels that I've outfitted with cages from D-Link to convert the SFP ports into gigabit Ethernet ports. My reason for doing this is because I'm eventually going to be doing some modification on the data coming across an Ethernet line, but for now I figured I'd start simple (since this is my first experience with the Stratix FPGA) and have the board forward data. That is, one SFP port will be connected to a switch, the other to a gigabit Ethernet card, and if everything works the gigabit Ethernet card will be able to play nice with my network (port A receives data and transmits it back out on port B, port B receives data and transmits it back out on port A). I've hit a few snags and in trying to debug realized that I made an assumption about the way the serdes is working that I'm not entirely sure is accurate. I've been trying to get some confirmation on this by going through the reference manual for the Stratix II GX, but so far have been unsuccessful in that endeavor. So, here's the question:  If I use the alt2gxb mega function to set up the transceiver as a two channel device using the GIGE protocol and a channel width of 8 bits, how will the data be collated in the serial to parallel conversion? It is my impression that the information coming in on the rx_datain lines will be converted into one byte for each line, and the rx_dataout line will contain the deserialized result of one channel in the lower byte, the deserialized result of another channel in the upper byte. Does anyone know if that assumption is correct?  Thanks in advance.

[Altera_Forum]

Suggestion. Try simulating just the receiver in a basic design with the output of the receiver brought out to pins. This will tell you the data bit order for the received data. You could also use SignalTap II to analyze the internal nodes of the receiver in your design real time on the board. Like a logic analyzer that is able to probe the internal nodes.

[Altera_Forum]

I have considered trying that, but am trying to save it as a bit of a last result. The gxb block is assuming that the input it's receiving (the bitstream from the SFP receivers) has already been 8b10b encoded, so if I were to bring the receiver output directly to a pin, it would be after going through the 8b10b decoder (which is internal to the block created by the gxb mega function, and as such to my knowledge unaccessible), which would require me to have either a good enough understanding of 8b10b encoding to decode the test input by hand or a tool for automatically decoded 8b10b messages, both of which I unfortunately do not have :( 

 Thank you for the suggestion, though. I'm hoping to avoid getting too deep into the actually encoding/decoding schemes that GIGE uses, but it looks like that might just be an unavoidable consequence of working with the things.  -Jordan Wills

[Altera_Forum]

Jordan,  

 In that case I would do a sample design without 8b10b encoding. Compile and simulate to see the bit order is as you understand it.

[Altera_Forum]

I had completely forgotten that the 8b10b encoder of the stratix could be bypassed... thanks, I'll give that a try =) 

 Much appreciated, Jordan