Stratix III DE3 and DDR2

[Altera_Forum]

Hello, 

 I am using the Terasic DE3 development board to create a Qsys SoC with a NIOS2, DDR2 memory (for an 1 GB RAM SODIMM module). I am following Terasic's pinout for all the DDR2 pins, but timing isn't being met for Read and Write as Altera complains about the following:  Critical Warning: Warning (307018): Memory clock pin mem_clk[0], mem_clk[1] must be placed on the same edge of the device Critical Warning: Warning (307020): mem_clk[0] was placed on the right edge of the device Critical Warning: Warning (307020): mem_clk[1] was placed on the bottom edge of the device Critical Warning: Read Capture and Write timing analyses may not be valid due to violated timing model assumptions  I also notice when I try to read and write to my memory, on occasions it gives garbage and I suspect its this timing that is not correct.  Anybody have any experience with this or any clues on what I could try?  Salman

[Altera_Forum]

hellow,i am using de3 board these days but i encounter some problems.when i read the data from ddr2,it seems that the output data does not match the data i write in .if you successfully finish the ddr2 data transfer on de3 board,could you send me you successful program or or instruction.my email is 1322826341@qq.com

[Altera_Forum]

--- Quote Start ---  hellow,i am using de3 board these days but i encounter some problems.when i read the data from ddr2,it seems that the output data does not match the data i write in .if you successfully finish the ddr2 data transfer on de3 board,could you send me you successful program or or instruction.my email is 1322826341@qq.com  --- Quote End ---    I will give it to you soon. I have been busy with some work. Hopefully in the next few days...  Salman

[Altera_Forum]

Hi,I also meet this problem.I use the DDR2 in DE3 board with IP. But there are some problems with it.it seems that the output data does not match the data i write in.Can you give a successful program?Thanks very much!my email is 1165366869@qq.com.

[Altera_Forum]

Hi,I encounter same problems. I used the DDR2 IP in de3 board.but the output data is not right.Could you give me a successful program.My email is yutaohurry@gmail.com.Thanks very much!

[LaiMickey]

Me too.

But I think we can ignore this Critical Warning.

The pin locations of mem_clk[0] and mem_clk[1] are the DDR2 SO-DIMM  socket pins.

They solder to the FPGA pin. Thus, we can not change the pin locations of mem_clk[0] and mem_clk[1].

The problem is somewhere else. 😕

LaiMickey