Stratix III Dynamic Phase Shifting

Altera_Forum · ‎03-04-2009

Hello :)

I am having trouble with using the Dynamic Phase Shifting feature of our Stratix III FPGA.

I have a situation as described from Section 6-62 of the Stratix III handbook:

A PLL with 2 output clocks of the same frequency, and I wish to step through the phase of the first one (c0).

ie, PhaseUpDown = '1', PhaseCounterSelect = "0010", PhaseStep is pulsed high for 2 scanclk cycles per step.

This is the process I use to step the phase to a desired offset:

  -- if phasedone = '1', and current_steps /= desired_steps, phase_step = 1.
  DO_STEPS : process (clk, reset_n)
  begin  -- process DO_STEPS
    if reset_n = '0' then               -- asynchronous reset (active low)
      current_steps <= (others => '0');
      PhaseStep     <= '0';				
      count         <= (others => '0');
    elsif rising_edge(clk) then         -- rising clock edge
      count <= count + 1;
      if count = "01" then
        if current_steps /= desired_steps and PhaseDone = '1' then
          PhaseStep <= '1';	 
	  -- loop phase steps back to 0 after a full 360 degrees.
          if current_steps = c-1 then
            current_steps <= (others => '0');
          else
            current_steps <= current_steps + 1;
          end if;
        end if;	 
      -- hold PhaseStep high for the extra clock cycle.
      elsif count = "10" and PhaseStep = '1' then
        PhaseStep <= '1'; 
      else
        PhaseStep <= '0';
      end if;
    end if;
  end process DO_STEPS;

Attached is an image of my simulation output - showing the phase happily stepping through.

My problem, as you may expect, is that I don't get this behaviour when I run the design on the hardware.

My outputs DO 'lock' correctly, and are at the correct frequency, and I DO get an appropriate 'PhaseDone' output, BUT I get NO phase shifting behaviour at all.

Has anyone else made a phase shifting design using the Stratix III?

Altera_Forum · ‎04-10-2014

i guess the reason why nobody responded is that you kinda did everything correctly and it should work. i just made it work today so i thought to share some my newly hatched experience.

first, take a look at this: http://niosii.com/support/kdb/solutions/rd04282008_233.html

second, try outputting all the clocks on your PHASECOUNTERSELECT configuration (here is cyclone's http://www.altera.com/literature/hb/cyc3/cyc3_ciii51006.pdf page 32,33) .

third, are you sure that during 2 clock cycles PHASESTEP is high? if it's high during only one cycle nothing will happen. check the PHASEDONE signal if it's constantly high the your pll doen't even tries to do anything.

and fourth, sometimes your phase shift resolution step is so low, that you don't catch the thing that it actually does shifts but very slowly. if you use encoder, turn it a lot. or go to pll dynamic phase shift configuration bar in the pll megafunction and rise the increment step to maximum (it often times is not more than 2degrees.)