Stratix-III FPP configuration issue with temperature

[Altera_Forum]

I configure an Stratix III device from a processor using FPP configuration mode. It works properly at ambient temperature but it fails at 50°C. 

I would think that it could be a problem of setup or hold between config data and DCLK, but setup is almost 60ns (compared to minimum 5ns required) and hold time is even longer. DCLK pulses are 60ns > minimum 4ns nCONFIG pulse is longer than 2us, and nCONFIG to DCLK is longer than 100us.  So I think is compliant with datasheet specs. When the ambient temperature increases the config fails with nSTATUS going low before the config process has finished. The higher the temperature the shortest the time between nSTATUS going high and low. If add a delay between configuration data writes the time to failure is longer, but so far I haven't been able to make it work at 50°C, and the configuration time becomes too long, about 40 seconds, when by specs is supposed to work at 100MHz. Anybody has an idea what could be going wrong? Thanks,

[Altera_Forum]

I found the issue and it was not related with FPGA FPP configuration timings but with reading configuration data from a Flash in burst mode. The burst accesses to the Flash where too short and failures were produced when temperature increased.