Stratix III JTAG/POR Issue

[Altera_Forum]

Greetings, 

 I'm working with a Stratix III FPGA (EPSL70F484) on a custom PCB configured in a JTAG / AS configuration with a EPSC16 and ran into a nasty problem. When I first powered up the board, I could initialize the JTAG chain, but eventually the chain would not initialize (sometimes it will, but only very rarely, and just after the board is powered up).  At first I thought it was a temperature issue (the board got very warm to the touch), but I've disabled enough of the other components that nothing gets warm except the FPGA. I also discovered the MSEL pins were not correctly chosen for the AS config, but that shouldn't matter for JTAG (right?). I don't think the EPSC16 is messing up the power-on configuration process, but I removed it from the board anyway (just in case). Incidentally, the EPSC16 part programmed fine with the USB-Blaster when it was on the board.  I've looked at the JTAG signals on an oscilloscope, and they look OK, but TDO (from the FPGA) seems to be stuck at GND (not a short - ohmmeter shows 260K resistance btw TDO and GND). nSTATUS and CONF_DONE remain low, which makes me think there may be a power on reset issue, but the supplies look OK, and I thought it shouldn't matter for JTAG anyway, as long as the voltages & pull-ups are ok.  I've tried about all I can think to do, so I was hoping for some assistance before calling Altera Support. Any suggestions would be much appreciated.  Alfred

[Altera_Forum]

Are there some multi-voltage application in your system?! May be this cause the JTAG out of work! You konw the configuration pins locate in several banks of the FPGA.

[Altera_Forum]

Yes, it is a multi-voltage design. I've attached a screenshot of the power supply portion of the board -- as you can see we're using several different IO voltages, but with respect to the JTAG interface, we're using 3.0V on VCCPGM and 2.5V on VCCPD1C (the bank from which the JTAG interface is powered, according to the handbook). 

 From what I recall in the handbook, this is all acceptable (although the 3.0V on VCCPD6A and VCCPD6C makes me nervous) but here's the weird part -- I tested the other prototype board and the JTAG chain enumerated (after not enumerating before)! This would seem to eliminate the power/JTAG interface design as the direct problem (unless the power configuration "breaks" the FPGA after a certain amount of time).  Now I'm leaning back towards a temperature related problem, but there are still some questions that temperature alone cannot answer (why are the config pins not in the expected state, why are the I/O lines sourcing/sinking current when they should be high impedance) -- has anyone seen this kind of behavior before?

[Altera_Forum]

Ok, I thought about my last post a bit more (took a walk) and remembered that the Stratix III I/O pins are tri-stated and weakly pulled up by default. I started thinking about how the two boards responded differently and remembered there were some problems with the layout which we discovered using the "bad" board and then fixed on both the "bad" and "good" boards (maybe the "bad" board's FPGA got damaged while troubleshooting). 

 Here's my diagnosis: I think the I/O lines are enabling other parts of the board that are not supposed to be on yet, causing the switching power supplies to work really hard to power those components that are processing bogus data (there are some RF/mixer components on the board, which also generate alot of heat), which makes the board really hot (thermal design is probably not as good as it could have been) and possibly causes the FPGA to either shutdown or not work properly.  The end result is a "bad" board that never works, and a "good" board that can JTAG for a minute before getting too hot. If you program it before then, everything is copacetic. Of course the Active Serial configuration problem doesn't help matters, but I think the answer to that is to drill out the GND via for the MSEL0 line and tie it high, like it should have been. In any case, I've got one board that can reliably JTAG, so I'm happy.  Thanks to Jerry and anyone who took a look at the thread and gave it some thought.

[Altera_Forum]

Hello Alfed, 

 I have a costum PCB with a EP3SL50F780 on it. Till now I had no problems with JTAG-configuration but I had this temperatur issue that u are describing... In fact, the FPGA temperature goes up till 50°C with a simple 'counterdesign' and till 70+°C with our complete Design. What temps do u have?   Yesterday, the JTAG-config stopped working. I thought it's because of the temperature issue but now I'm not so sure anymore...  Are u sure that ur I/Os are sinking/sourcing instead being HighZ? This would be wired but if u are sure it is the reason why your FPGA is getting hot.   regards, helac

[Altera_Forum]

helac, 

 Are you sure the board is functioning as expected? For my board, the thermal problem seemed to be caused a switching power supply powering high current components (that should have been off) using a buck/boost supply that wasn't boosting -- that generated alot of heat from switching losses and powering ICs that had noise for data.  I haven't done a temperature measurement, but it got hot enough so that you could only touch the FPGA for a few seconds before it became uncomfortable. Seems like your problem might be a little different than mine -- how fast are you clocking your design? Perhaps you may want to add a heatsink to the FPGA. It's certainly conceivable that heat caused the JTAG interface to to malfunction/shutdown/stop working, but I would try waiting until the board is cool, and try it again (or try programming using AS if possible).  Regarding the state of the I/O lines, they were definitely sourcing current (there were some LEDs on I/O lines that were partially lit). I remember reading somewhere (maybe in Quartus, or the documentation for Quartus) that the default configuration state of the FPGA I/O pins is tristated, and weakly high. I could have avoided the issue by programming the serial config flash on my board, but my MSEL pins were not configured properly, hence my original dilemma.  Alfred