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Valued Contributor III

Stratix III PLL Jitter Control



In my design using Stratix III FPGA, I have one dynamic reconfigurable PLL (top/bottom type). Beside setting up the parameters to generate output clocks [Fout = (Fin x M)/(N x C)], I would like to know more on how to control the jitter. I read the Altera HandBook I on other parameters such as VCO, charge pump, loop filter that can have effect on the output clock jitter. But I'm still not clear on how to set these paramters (one time or dynamically) to achieve the optimized control of jitter. Can anyone help... 


Thank you,....Daven
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