Stratix III. Problems with JTAG and Fast AS

[Altera_Forum]

Hello all! 

 I have problems with Stratix III configaration on self-made PCB. We use Fast AS with EPCS64 and JTAG.  Download cable: USB Blaster (not original ALTERA cable).  1. JTAG detects chain only when EPCS64 is erased. When EPCS64 is loaded, JTAG has an error with detecting the chain.  2. It seems like FPGA always try to load the configuration. May be it goes to POR periodically, but all powers look fine.   Where should I search the source of trouble?  Best regards, Pavel  P.S. I've added the schematic of FPGA power and configuration chains.

[Altera_Forum]

You can set the option "Halt on-chip configuration controller" in Quartus programmer to prevent reconfiguration in JTAG mode. There are probably other errors, e.g. missing pullups at configuration control pins, but this option should allow JTAG programming though.

[Altera_Forum]

Thanks for reply! 

   --- Quote Start ---  You can set the option "Halt on-chip configuration controller" in Quartus programmer to prevent reconfiguration in JTAG mode.  --- Quote End ---    We've tried your recommendation. Nothing's changed.   I will check pull-ups once more.  Best regards, Pavel

[Altera_Forum]

Another possible reason is this: If your JTAG circuit is very sensitive to on-board generated interferences, it may fail when the design is active and generated interfering signals. Insufficient supply decoupling and FPGA ground connections, long JTAG traces, too high TCK pulldown-resistor are known issues in this regard.

[Altera_Forum]

Thank you for the clue... We've found one wrong pull-down. TCK was with 10 KOhm instead of 1 KOhm. But the problem remains. JTAG traces have 2-3 inches length. Design is very very simple. 2 LEDs are driven by constant high level. No other logic. 

I suppose it's power and/or ground problem.

[Altera_Forum]

Hard to decide from a distance. A trivial cause could be from a I/O pin inadvertently shorted to a JTAG pin. Quartus JTAG chain debugger can help to trace the apparently broken chain.

[Altera_Forum]

Thank you for you advice.  

We'll check it once more.  I've added the schematics of FPGA power and configuration to the first post. Could you check it?  Best regards, Pavel

[Altera_Forum]

You may reduce the resistor value for nCE. It has to be low for successful JTAG programming. 

Regards, Heiko

[Altera_Forum]

A nCE pulldown of 10K is according to Altera AS programming circuit examples and supposed to work correctly. But there may be a problem if the line is picking up interfering signals. A small capacitor (e.g. 100 pF) in parallel should also help in this case. 

 P.S.: Not detecting the JTAG chain indicates severe JTAG hardware problems and usually won't be caused by interfering signals or slightly to high resistor values. It would be a different case, if you notice configuration problems with large images. If the chain discontinuity is a permament problem, you first should check individual JTAG signals with Quartus JTAG debugger and an oscilloscope. However, if all input signals seem OK and TDO simply doesn't response, there may be a more general problem of power-on-reset and device initialisation. But I'm not using Stratix III and don't know about particular issues.

[Altera_Forum]

We've tried a 100 pF capacitor in parallel to nCE. Nothing's changed. 

 Could it be interference with 110 MHz LVDS line near (~1 cm) EEPROM? We are going to check it today.