Stratix III alt_lvds Timing Requirements not met in speedgrade C2

[Altera_Forum]

Hi there, 

 it's me again with the Stratix III ;) I'm currently using a Stratix III with speedgrade C2 (the one mounted on the Altera Stratix III DSP Kit) and want to use the alt_lvds function in a small test design for automatic BER measurement. Using serial link rates from 500 Mbit/s to 1100 Mbit/s work fine but if I want to use 1500 Mbit/s (in speedgrade C2, 1600 Mbit/s are defined as max.) the Analyzer throws some errors regarding the timing: "Critical Warning: Found minimum pulse width or period violations. See Report Minimum Pulse Width for details."  => I checked the Time-Quest report and found a negative slack on the high speed clock from the serial receiver clk[0]; This clock is used within the alt_lvds block only (internal PLLs).  The minimum width would be 0.666 ns (equals to 1500 Mbit) but Quartus expects a width not less than 0.8 ns (=> results in negative slack), which is exactly the same value as specified in the preliminary Stratix III datasheets! (in the preliminary datasheet it was limited to 1.25 Gbit for all speedgrades)  Does anyone have a solution to this problem? I have to use the 1500 Mbit/s and the C2 speedgrade also specifies 1600 Mbit which should work. Is there a known bugfix for this?  kind regards, lestard

[Altera_Forum]

Are you using Quartus version 8.1? The timing model of some Stratix III devices was updated in version 8.1.

[Altera_Forum]

Oh I'm sorry, I forgot to mention the version I'm currently using. 

 Yes it is Quartus 8.1 on an 64bit machine.  regards, lestard

[Altera_Forum]

Hi lestard, 

 I'm having a similar problem using Stratix III with a DDR3 SDRAM interface. In AN436 (page 53) I found the following notation:   "The Quartus II software v8.1 has a bug that results in an incorrect calculation for the toggle rate for differential I/O standards."   I'm going to submit a service request. Maybe you could do likewise, and we'll see if there is a patch for this in advance of the next Quartus release.   BTW, do you know when the next Quartus release is scheduled?   Regards, Ron     

[Altera_Forum]

--- Quote Start ---  BTW, do you know when the next Quartus release is scheduled?  --- Quote End ---    http://www.altera.com/corporate/news_room/releases/products/nr-quartusiiv90.html?f=hp&k=wn2 says, "A beta version of the Quartus II software version 9.0 is currently available for download. On March 9, 2009, Altera will release the 9.0 production version of Quartus II software, the ModelSim Altera Edition and the ModelSim Altera Starter Edition."

[Altera_Forum]

Hi, 

Can you try to do this: Open TimeQuest Timing Analyzer in Tool Menu. In Contrainsts Menu, choose Generate SDC file from QSF Add into *.SDC file these lines:  set_time_format -unit ns -decimal_places 3 create_clock -period 20 -name clk [get_ports {clk}]  set_clock_groups -exclusive -group clk  (clk is name of clock signal used in your design)  Open Setting project and add this *.sdc file into TimeQuest Timing Analyzer   Hope it works.