Hi,
I am using the Stratix IV GT 10.3125 Gbps Transceivers. The input reference clock to
the transceiver CMU blocks in 644.53 MHz. That get translated to 257.8125 MHz at 40-bit
FPGA fabric interface.
I am using the tx_clkout[0] as an input to PLL to clock all of my transmit path logic. This works fine. The problem is when I try to use the recovered clock rx_clkout[0] as an input to another PLL to generate all my receive path clocks (I need this to avoid clock compensation) the quartus II tool gives error that it can only be through dedicated clock/PLL pins.
Is there a way to use the rx_clkout as an input to PLL. The strange this is that it allows the tx_clkout to be used as a PLL input. Any suggestions ?
One more thing. Anyone has looked at the AN_570 for 100G Ethernet clocking. The clocking structure shows that they change the clock domain at the Gearbox FIFOs. How is that possible as we can't do Idle insertion/deletion at that point for clock compensation ?
Thanks,
Haris
Thanks,
Haris
