Stratix IV GX altgx reconfiguration

[Altera_Forum]

I've got a project that I'm porting from Stratix II GX to Stratix IV GX. Basically I'm using all the transceivers in a Quad. I'm using both TX PLLs in the Quad. I need to dynamically select which PLL drives the output of each channel in the Quad. 

 Now I had no problem doing this with Stratix II GX.   I've configured the ALTGX instance for dynamic reconfiguration and enabled the alternate PLL. But with Stratix IV GX, Quartus seems to be ignoring the fact that the altgx instance is configured for multiple PLLs and dynamic reconfiguration. It lists both PLLs in the fitter report. But it merges all of the tx_clkout clocks from all four channels in the Quad into a single clock. And this despite the fact that I've selected the "Use the Respective Channel Transmitter Core Clocks" option in the megawizard. Also, Timequest seems to find all of the clocks associated with both PLLs. But only finds a path from PLL0 to the tx_clkout signal. It does not find any paths from PLL1 to tx_clkout. And of course, Timequest has merged all of the tx_clkout signals from each channel into 1 signal.  Any ideas? Am I missing something?  Thanks, Jake

[Altera_Forum]

Hi Jake, 

Did you ever resolve this issue? I am having a similar problem with a Stratix IV ALTGX transceiver. But I'm not sure if I'm putting in the correct timing constraints in the first place. I just put a constraint on the input ref clk and then do "derive_pll_clocks". Is that what you're doing?  I notice there only seems to be one tx_clkout signal when I have five channels and am expecting five tx_clkout signals.  Does anyone have experience with this?

[Altera_Forum]

I should have followed up. In my case, Altera has acknowledge there is a bug in Quartus where it is not correctly discovering that the output clocks are independant. 

 Supposedly it may be fixed in 10.0 but I haven't tried it yet.  Jake