Stratix SDM Encryption Accelerator?

[LowLevelGuy]

The Stratix 10 white paper states that HW based cryptography acceleration is available through the SDM mailbox mechanism.   However, I cannot find any documentation or code that describes such.   Where can I find further details?

https://www.intel.com/content/www/us/en/content-details/650483/secure-device-manager-for-intel-stratix-10-devices-provides-fpga-and-soc-security.html

The SDM uses these blocks during the configuration (and reconfiguration) process; however, these acceleratorblocks are also available for user applications after device configuration with appropriate licensing through the Intel Quartus® Prime software. For example, designs could use these blocks for encryption/decryption of data traffic in user applications, as well as authenticating messages to and from the FPGA. Service requests to these blocks come through either the FPGA fabric or the ARM* Cortex*-A53 HPS system to a request mailbox in the SDM, which instructs the blocks to perform encryption, decryption, hashing, signing, or signature checking functions.

I cannot find any reference to this functionality in either the "Intel® Stratix® 10 Device Security User Guide" nor in the "Mailbox Client Intel FPGA IP User Guide".

[Fakhrul]

Hi LowLevelGuy,

We sincerely apologize for the inconvenience caused by the delay in addressing your Forum queries. Due to an unexpected back-end issue in our system, your Forum cases, along with others, did not get through as intended. As a result, we have a backlog of cases that we are currently working through one by one.

Please be assured that we are doing everything we can to resolve this issue as quickly as possible. However, this process will take some time, and we kindly ask for your patience and understanding during this period. The cases will be attended by AE shortly.

We appreciate your patience and understanding, and we are committed to providing you with the best support possible.

Thank you for your understanding.

[Fakhrul]

Hi LowLevelGuy,

Can you provide the link of the white paper?

Regards,

Fakhrul

[LowLevelGuy]

Sorry, I missed your reply as all of Intel's emails are considered Junk by Office365.

This is the whitepaper.  See page 2,  "Encryption Support Hardware".    

All I want to do if to find out how to use the stated features as no public documentation exists for them.

https://cdrdv2-public.intel.com/650483/wp-01252-secure-device-manager-for-fpga-soc-security.pdf

Excerpt below, (emphasis added):

The SDM uses these blocks during the configuration (and

reconfiguration) process; however, these accelerator

blocks are also available for user applications after device

configuration with appropriate licensing through the Intel

Quartus® Prime software. For example, designs could use

these blocks for encryption/decryption of data traffic in user

applications, as well as authenticating messages to and from

the FPGA. Service requests to these blocks come through

either the FPGA fabric or the ARM* Cortex*-A53 HPS system

to a request mailbox in the SDM, which instructs the blocks

to perform encryption, decryption, hashing, signing, or

signature checking functions.

[Fakhrul]

As we haven't received a response to our previous notification, this thread will be transitioned to community support. We hope all your concerns have been addressed. If you have any new questions, please feel free to open a new thread to receive support from Intel experts. Otherwise, community users will continue to assist you here. Thank you.