Stratix V PLL Location Congestion

[Altera_Forum]

Hi, 

 I'm working on a design based around a Stratix V GS D6 FPGA. In the design there are two UniPHY memory controllers being implemented on the bottom of the chip. These two controllers will run at different frequencies with different reference clocks. I am using Quartus 14.0.  I was planning on using the bottom centre Fractional PLLs for this but it seems that I may have misunderstood something. From the datasheet there are 24 FPLL locations, including two in the bottom centre of the device:  FRACTIONALPLL_X92_Y11 FRACTIONALPLL_X92_Y2  Fitting of my design fails because of PLL congestion - the fitter can't find space for both FPLLs. One is placed fine in location FRACTIONALPLL_X92_Y2. For the other it gives an error saying there is no valid location and gives a list of 6 locations it has considered for the FPLL, one in each of the four corners (not possible due to the reference clock dedicated routing), one at the top centre (again not possible for the same reason), and one at the bottom (FRACTIONALPLL_X92_Y2) which cannot be used because it is already in use.  I am trying to understand why if there are two FPLL locations in the bottom centre, does it only consider one of them. It seems that FRACTIONALPLL_X92_Y11 is ignored.  I can't find anywhere in the device handbook which explains why FRACTIONALPLL_X92_Y11 is not considered for placing the PLL.  The bottom left corner is an option (FRACTIONALPLL_X0_Y1) as on the Dev board I am using there is a second clock with the same frequency I require which is connected to a clock input which can feed this PLL so I can use that instead as a ref clock. The trouble is when that one is used I get a timing error in the memory controller with a setup and hold violation: +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Setup: rld_mem_ck ; +--------+-----------------------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------------------------------------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+-----------------------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------------------------------------------+-------------+--------------+------------+------------+ ; -0.020 ; top|rld_memory|p0|umemphy|uio_pads|dq_ddio.ubidir_dq_dqs|altdq_dqs2_inst|dqs_select|clkout ; rld_mem_dk ; top|rld_memory|p0|umemphy|uio_pads|dq_ddio.ubidir_dq_dqs|altdq_dqs2_inst|dqs_select|clkout_leveling_clock_dk_0 ; rld_mem_ck ; 5.000 ; 3.012 ; 3.332 ; +--------+-----------------------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------------------------------------------+-------------+--------------+------------+------------+ +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Hold: rld_mem_ck ; +--------+-----------------------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------------------------------------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+-----------------------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------------------------------------------+-------------+--------------+------------+------------+ ; -0.078 ; top|rld_memory|p0|umemphy|uio_pads|dq_ddio.ubidir_dq_dqs|altdq_dqs2_inst|dqs_select|clkout ; rld_mem_dk ; top|rld_memory|p0|umemphy|uio_pads|dq_ddio.ubidir_dq_dqs|altdq_dqs2_inst|dqs_select|clkout_leveling_clock_dk_0 ; rld_mem_ck ; 0.000 ; 3.550 ; 3.172 ; +--------+-----------------------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------------------------------------------+-------------+--------------+------------+------------+    Could someone explain why FRACTIONALPLL_X92_Y11 is not usable for this?

[Altera_Forum]

Never mind, found an answer to why the centre PLL can't be used. 

https://www.altera.com/support/support-resources/knowledge-base/solutions/rd12032013_135.html

[Altera_Forum]

Hi TCWORLD, 

 Thanks for sharing the solution.

[Altera_Forum]

Thank you for sharing the root cause.

[Altera_Forum]

It answers the question of why both PLLs can't be in the centre, but I am still stuck with the timing errors on the RLDRAM (no matter what frequency I set the memory clock to, I get exactly the same setup/hold violations with exactly the same number of picoseconds of slack.