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Stratix10 25G E-Tile IP


I used E-tile IP with 25G, I got some problem like follow:

In Quartus, the 25G reference clock is set to 322Mhz, regardless of the external clocks 312.5 and 322, it can work normally, but when the software is set to 312.5Mhz and the external setting is 312.5Mhz, the normal internal LoopBack cannot be used.

there is someone can help me or how to debug that .


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As I understand it, you are observing some internal loopback issue with the E-tile Native PHY at 25G when refclk frequency is set to 312.5MHz. To facilitate further debugging, just would like to check with you on the following:


1. Mind further elaborate on the internal loopback cannot be used observation?


2. Just wonder if the external loopback still working?


3. Mind share with me the specific steps that you are using to enable the serial loopback?


4. Just wonder if you have had a chance to try with XCVR toolkit to see if the serial loopback is working?


5. Mind share with me which Quartus version and device that you are using?


6. Mind share with me the .ip file of the Native PHY instance so that I can have a better understanding of the configuration.


7. I believe you have done this but just to double check for isolation if you have had a chance to use oscilloscope to check on the refclk frequency on-board to ensure 312.5MHz?


Please let me know if there is any concern. Thank you.



Best regards,

Chee Pin

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