Stratix10 Dx P-tile PCIe flow control

[GDeXi]

   hi, thanks for your help. I'm try to build own pcie adptor base on s10dx P-tile ST IP. I get some confuse for flow control in P-tile st ip user guide

   when i set TLP pkg to st  ip, usually I need check where opposite end has enough credit to accept my pkg. but i don't understand how the st ip describe about flow control:

For example, if the remote Receiver advertises an initial Non-Posted Header (NPH) FC credit of 0xFFFF, after it receives a MRd request, the NPH FC credits value increments by 1 and rolls over to 0x0000. The tx_cdts_limit_tdm_idx_o[2:0] signals determine the traffic type(From user guide

).

   would please tell me there is additional logic to check flow control? if yes, how i get credits for opposite end form st ip user guide description, if not, the st ip core would check it self? and pull down ready signals for delay transmission?

[Rahul_S_Intel1]

Hi ,

 The TX will work as same as RX Flow control. I am copying the descript from the ug for your reference.

The RX flow control interface provides information on the application's available RX
buffer space to the PCIe Hard IP in a time-division multiplexing (TDM) manner. It
reports the space available in number of TLPs.
The RX flow control interface is optional and disabled by default in the IP GUI. If
disabled, it indicates that there is no limit in the application RX buffer space

Pag no: 52

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_ptile_pcie_avst.pdf

[GDeXi]

Sorry, I do not understand what your mean, could you please description it more clearly

[Rahul_S_Intel1 · Accepted solution]

Hi , 

Sorry for my confusion answer

Kindly find the inline answers.

  would please tell me there is additional logic to check flow control?

>>No ,The ip have the capability to verify the flow control