I'm planning to use several triple speed ethernet Mac IPs but as far as i could see, you can't use Tile transceivers to do that. So i tried to compile my design with TSE (lvds io with integrated serdes).
I managed to implement 8 tse at once but i could not with 16 of these as the fitter was unable to find enough IO to do that. I suspected that the number of IOPLL was unsufficient but i read there was 32 differentials of them.
I don't know how to fix this problem.
Also, i ask if there is way to use H-Tile transceivers to implement SGMII protocol. I know it sounds weird to implement such a low speed interface but i need the large computing capabilities of the S10MX.
Thank you for your reply.
i am using the 1SM21BHU2F53ES2 for test purposes (Stratix 10 MX FPGA Development Kit). I didn't assign any IOs at first as the planner can do it automatically.
see the error i get during plan stage :
I was asking about the Tile transceivers because i downloaded an example design from INTEL (Stratix 10 SoC fpga devkit, schematic p.13) where IOs for the triple speed Ethernet were connected to dedicated transceivers(GXBR4M_RX_CH4P, GXBR4M_REFCLK4P for example).
Thank your very much dlim
1) For the fitter error
2) For TSE IP connecting to XCVR channel
1) I found a limit of 14 TSE IPs. After this number, the fitter could not find a suitable scheme for pin assignements. (it seems you can drive only 1 PLL per bank, i think i read this limitation somewhere in a datasheet )
I sent you the .qar file of my early design with 15 TSE LVDS IO.
2) There is no design example provided with S10 soc kit which instanciates a TSE IP with LVDS IO. However, you can see in golden_top design (see the attached qar) that sgmii pins are linked to gxb transceivers. Those ones may be used with a 1G/10G phy design but there is no example which explicitly shows how it has been implemented.
Maybe, you can tell me more about this.
Have a nice day,
Thanks for sharing the design file. Pls see my reply below.
sorry for the missing .qsys in the qar file. Anyway, now i know how many TSE i can implement with lvds io. Thank you for that.
For the multi-rate design, i was checking this option as an alternative. The X557 AT4 phy seemed to fit my needs, but i am quite lost in the datasheet (KR, sgmii, connect to lane 0 for sgmii, ok but what if i want to use 10G, and so on) . I did some research on google and multiple vendors used it for their networking products.
So, my last inquiry would be : where can i find some help to interconnect the multi rate phy on s10 and the x557 phy as quickly as possible? 😅
For now, i have multiple distant FPGAs with 88E1111 phy which can run at "only" 1Gbps.
Thank you very much dlim,
Have a nice day.
Thanks for showing interest with Intel product.