Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Need Forum Guidance? Click here

Search our FPGA Knowledge Articles here.
19090 Discussions

Synchronization of data, control and clock inputs in QuartusII

Honored Contributor II

Hey everyone, 


i am getting a data(4 Bit), a control(1 Bit) and a clock signal from the Cyclone V pins which are driven by extern sources.  

These signals are misaligned and i want to align the control and the data signals to the extern clock signal in my FPGA design.  


Are there any Altera/QuartusII provided IP-Cores available to this task? What is the best method to align them? 


The deskew isn't static, so timing constrains are probably not the right solution. 

I am using Cyclone V and QuartusII 2017. 


Every help is very appreciated, thanks in advance. 


Best regards
0 Kudos
1 Reply
Honored Contributor II

Add a PLL and choose one of the available clock compensation options.