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Synchronization of data, control and clock inputs in QuartusII

Altera_Forum
Honored Contributor II
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Hey everyone, 

 

i am getting a data(4 Bit), a control(1 Bit) and a clock signal from the Cyclone V pins which are driven by extern sources.  

These signals are misaligned and i want to align the control and the data signals to the extern clock signal in my FPGA design.  

 

Are there any Altera/QuartusII provided IP-Cores available to this task? What is the best method to align them? 

 

The deskew isn't static, so timing constrains are probably not the right solution. 

I am using Cyclone V and QuartusII 2017. 

 

Every help is very appreciated, thanks in advance. 

 

Best regards
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Altera_Forum
Honored Contributor II
161 Views

Add a PLL and choose one of the available clock compensation options.

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