I am using a MAX V CPLD to drive a chain of serial ADCs. If I have multiple IO pins driven by the same internal clock signal, what might I expect for pin-to-pin clock skew?
Can be hundreds of ps or a few ns, depending on the routing.
Are those I/O pins just copies of the clock signal or are they output of registers driven by the clock? In any case, build a small project, compile it and see the TimeQuest report.
The output clocks might be either registered outputs or replicas of the clock. I have not designed the logic yet.
I did exactly what you suggested and found that pin placement makes a large difference if I want to minimize skew between outputs. Overall input-to-output delay was about 8-12ns within the same bank. The MAX V datasheet also has useful information on propagation delays.
