SystemVerilog Coding Style

[Altera_Forum]

Hello, 

 I have what might seem a strange question - but as you might be able to see from my other posts, I am a young, inexperienced designer and am currently at University taking my major individual project. I am creating a hardware implementation of AES-128 algorithm in SystemVerilog, and as of tonight, have finished my first implementation and am now looking for any optimisations.  I have coded 2 different versions of an Encryption Core...however both use different coding styles. They both operate the same, and simulate the same.  One style uses more functions, and the other uses more ASSIGN statements to generate the combinational logic. The code that uses functions has an 10MHz higher FMAX on Quartus once synthesised...and im not sure why?  I was wondering whether I could get some feedback on each style (files should be attached), and general best practices.  *I dont expect you to understand the AES algorithm, and yes I havent uploaded the "KeyExpansion" module so that code wont compile*  Any replies would be appreciated :)

[Altera_Forum]

FYI: Formatting may be lost once saved as .txt so use Notepad++!

[Altera_Forum]

The style to use is the one that is most readable and understandable, and explainable.  

Using the assign statements is generally more "structural " in nature, where are using functions is more behavioral, and is preferred in my opinion. Why a speed enhancement with functions? Probably because of optimization on larger blocks in the functions.  Ben Cohen systemverilog.us