Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
21592 ディスカッション

T_ramp time question on Cyclone10 LP device

xytech
新規コントリビューター I
1,756件の閲覧回数

Hi ,

We use 10CL055YU484C8G. MSEL sets as Standard POR mode, datahseet reqiures ramping time of power supply to be within 50us~50ms.

Is this requirement apply for each single power rail's t_ramp or Total t_ramp time of all rail?

Thanks!

 c10-tramp.png

0 件の賞賛
1 解決策
Rahul_S_Intel1
従業員
1,404件の閲覧回数
Hi, Do you mean that the sum of all power rails' t_ramp should be within 50us-50ms? Yes

元の投稿で解決策を見る

6 返答(返信)
xytech
新規コントリビューター I
1,404件の閲覧回数

UP​

xytech
新規コントリビューター I
1,404件の閲覧回数

another question is , if the power rail ramps up too fast (<50us) or too slow(>50ms), what may happen? Thanks.

We now have a LDO desgined for VCCA_PLL_2V5 for 10CL055YU484C8G , whose ramp time is rather short, about 30us or so. That's is my worry.

 

xytech
新規コントリビューター I
1,404件の閲覧回数

up​

Rahul_S_Intel1
従業員
1,404件の閲覧回数
Hi, Total supply attached to the POR monitoring supply
xytech
新規コントリビューター I
1,404件の閲覧回数

Hi RSree,

Do you mean that the sum of all power rails' t_ramp should be within 50us-50ms? Thanks.

Rahul_S_Intel1
従業員
1,405件の閲覧回数
Hi, Do you mean that the sum of all power rails' t_ramp should be within 50us-50ms? Yes
返信