Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
Need Forum Guidance? Click here

Search our FPGA Knowledge Articles here.
18972 Discussions

T_ramp time question on Cyclone10 LP device

xytech
New Contributor I
492 Views

Hi ,

We use 10CL055YU484C8G. MSEL sets as Standard POR mode, datahseet reqiures ramping time of power supply to be within 50us~50ms.

Is this requirement apply for each single power rail's t_ramp or Total t_ramp time of all rail?

Thanks!

 c10-tramp.png

0 Kudos
1 Solution
Rahul_S_Intel1
Employee
140 Views
Hi, Do you mean that the sum of all power rails' t_ramp should be within 50us-50ms? Yes

View solution in original post

6 Replies
xytech
New Contributor I
140 Views

UP​

xytech
New Contributor I
140 Views

another question is , if the power rail ramps up too fast (<50us) or too slow(>50ms), what may happen? Thanks.

We now have a LDO desgined for VCCA_PLL_2V5 for 10CL055YU484C8G , whose ramp time is rather short, about 30us or so. That's is my worry.

 

xytech
New Contributor I
140 Views

up​

Rahul_S_Intel1
Employee
140 Views
Hi, Total supply attached to the POR monitoring supply
xytech
New Contributor I
140 Views

Hi RSree,

Do you mean that the sum of all power rails' t_ramp should be within 50us-50ms? Thanks.

Rahul_S_Intel1
Employee
141 Views
Hi, Do you mean that the sum of all power rails' t_ramp should be within 50us-50ms? Yes
Reply