TSE MAC IP Waitrequest function

[Altera_Forum]

hi, 

  am trying to capture MAC Control interface signals on TSE ip in my design on signal tap, i put the proper address,writedata,write signals with proper delays , then also i get waitrequest signals high, then i tried with only address and writedata , write,clk(mac_clk) signal i made low then also i get waitrequest continuously high what may be the reason.  This waitrequest depends on what and when it will go low  

[Altera_Forum]

I was experiencing some troubles with the TSE's transceiver based SGMII interface's receiving packets, but transmitting only damaged packets. See references below. 

 http://www.altera.com/support/kdb/solutions/fb90522.html http://www.altera.com/support/kdb/solutions/fb61021.html  Therefore I switched to the RGMII mode of the TSE MAC, but now there is a new problem where the processor is unable to access the registers in the TSE MAC. Looking closer in signal tap I see that the wait request of the TSE MAC is high before any software, or hardware, makes the first Avalon MM access to the TSE MAC. See attached signal tap image. I also see some, probably relevant, messages like this during the build (despite there appearing to be reasonable clocks attached to the design).  Warning (15400): WYSIWYG primitive "tse_mac_inst|altera_tse_top_gen_host:top_gen_host_inst|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_tx_counter_cntl:U_TXCNT|altera_tse_dpram_8x32:U_ARRAY_2|altsyncram:altsyncram_component|altsyncram_ehq1:auto_generated|ram_block1a7" has a port clk0 that is stuck at GND  The wait request signal goes down the rabbit hole into the encrypted part of the TSE MAC so its difficult to move forward on this.  Any suggestions concerning what I might have done to cause this issue are appreciated.  I am using Quartus 12.1 SP1.  https://www.alteraforum.com/forum/attachment.php?attachmentid=7172

[Altera_Forum]

I believe the problem is that you don't have the RGMII tx_clk port connected correctly.

[Altera_Forum]

--- Quote Start ---  I believe the problem is that you don't have the RGMII tx_clk port connected correctly.  --- Quote End ---    Thanks Ted. That was definately the issue.   BTW, I found this reference which covers also the timing constraints for RGMII.  http://www.altera.com/support/examples/interfaces-peripherals/exm-tse-rgmii-phy.html