We are using PCIe and Transceivers in our project.
we have tested both separately for transceivers and PCIe.
We are able to access transceivers In separate project by using transceivers tool Kit (TTK) but
when same project integrated with PCIe we are getting error in TTK as
"Jun 14, 2022 4:23:23 PM com.altera.debug.core
SEVERE: TTK failed reading from PHY slave_4000, cannot enable TTK functionality for this PHY. Please verify the reconfig_clk is running and ensure this PHY is not stuck in reset."
Please help to solve the error.
is it expected behavior? if NOT how to solve the error?
From the error message, it's basically complaining about either you didn't provide reconfig_clk from your board or the transceiver is not released from reset properly.
- Can you double-check your reconfig_clk (100MHz to 125MHz) and verify your transceiver power-up sequence to ensure calibration is done and both PCS Tx_ready and Rx_ready signal are asserted ?
- Pls share with me your signal_tap file where you captured all the transceiver status signals from Transceiver PHY reset controller IP
- Another thing to watch out is did you provide clock frequency to FPGA clkusr pin as transceiver power-up calibration clock ?
- Another suggestion is pls reduce/disable your JTAG connection chain on board and also reduce the JTAG clock frequency from 24MHz to maybe 16MHz or 6MHz to see if it helps
- Please ensure the reconfig_clk and reconfig_reset of the transceiver PLL were connect to system clock and reset
Glad that your problem is solved. Although not much help I can provide.
Thanks for sharing with me your solution as well. With that, I am setting this case to close status at this time.
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