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SG0001
Beginner
456 Views

TX PHY Transceiver clock

Hi.

 

In my project I use Arria 10 FPGA.

I receive 9953.28Mbit/s stream on Transceiver and I need to retranslate it with the same speed(no idle). RX clock is not ideal, what is why I can`t use internal reference clock for TX.

As I understand, I need to use RX recovered clock as a clock for TX, but not sure how I can do that.

Is this OK, If I use parallel rx_clkout_clk as input for FPLL and connect to tx_serial_clk0_clk?

Or I need use high speed serial RX recovery clock from CDR as TX clock?

 

Best regards.

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3 Replies
SG0001
Beginner
37 Views

As I understand in ug_arria10_xcvr_phy(page 385), the local CGB is feeded by CDR, but I cant find clk output from CDR

2019-03-27 18_13_07-Window.png

CheePin_C_Intel
Employee
37 Views

Hi, Thank you for contacting us. Allow me some time to look into your issue. I shall come back to you with findings. Thank you for your patience. Best regards, Chee Pin
CheePin_C_Intel
Employee
37 Views

Hi, As I understand it, you seems to have some inquiries related to re-transmit of data using the same clock domain as the received data. For your information, the GXB refclk would need clean clock. Based on my understanding, you would need to feed the RX recovered clock to an external clock cleaner on board, then feed the cleaned clock back to the TX refclk. Please let me know if there is any concern. Thank you.
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