In my project I use Arria 10 FPGA.
I receive 9953.28Mbit/s stream on Transceiver and I need to retranslate it with the same speed(no idle). RX clock is not ideal, what is why I can`t use internal reference clock for TX.
As I understand, I need to use RX recovered clock as a clock for TX, but not sure how I can do that.
Is this OK, If I use parallel rx_clkout_clk as input for FPLL and connect to tx_serial_clk0_clk?
Or I need use high speed serial RX recovery clock from CDR as TX clock?