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I have a processor design that was generated using Quartus II 4.1, targetting a cyclone device. Recently I designed a board that used a cyclone II 2c35 and built the processor into the device (simply copied the appropriate files into the new project). This worked fine and the processor ran with no problems. I have just designed a board that uses a cyclone II 2C5 and when I fit the processor into this device I get strange problems. Depending on changes to other logic within the design the processor stops running. On sum builds the processor fails to run at all and on others it will run for a period and then stop. The build is reporting no timing errors so I am unsure what is causing this. I unerstand that the processor was generated unsing an old version of quartus specifically for the cyclone but this design works fine for the 2C35 so why not the 2C5. I have avoided re-generating the processor as I then run into problems building the code for the new processer in the latest version of IDE as the lwip has changed. Anybody have any suggestions?
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As I know that the 2C5 and 2C8 has only 2 clock control blocks and 2 PLLs while the rest of Cyclone II has 4 each. I'm not sure if your issue is with the clocking or not. That's the difference between 2C5 and 2C35 generally.
Anyway, you should regenerate your processor for the device that you are generating for.- Mark as New
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Thanks for the reply LTS,
Interestingly although I am using only one PLL I decided to remove it so that the clock input pin is connected directly to the processor and I no longer see any errors - not holding my breath though as this being the solution. With regard to generating the processor again, the problem with this is that the lwip changed from NIOSII 1.1 and when I create a new processor and come to compile the code in a later version of IDE I get errors concerning the read_phy_register command not existing. I have been on the nios forum, downloaded the lwip zip and installed it but still no joy. I will keep trying.
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