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Honored Contributor I

Terasic SDRAM controller burst length

Hello guys,  


For one of my project based on Altera DE2i-150 FPGA, I need to take input from D5M camera and store the image in the SDRAM and then I need to read the image data (for my application) from SDRAM in the format shown in the attached figure (basically in columns of 4), rather than the conventional raster scan fashion, process it and display on VGA..  


The available SDRAM controller (with dual ports each for read and write) written in verilog provided by terasic with the demo designs of de2i-150/115, writes and reads the data in the conventional raster scan fashion from SDRAM. So I need to modify SDRAM controller to read data in the particular fashion I mentioned. can anyone please provide me suggestions on the approach which i should take? 


The attached another image contains the top level interface to this SDRAM controller (dual port read and dual port write). I am trying to modify it or my application. There are inputs know as read & write lengths (which basically is the burst length of data written into sdram from write fifo's or read from sdram into read fifo) which I have highlighted in yellow (in the image), for 640x480 it's 8'h50 and for 800x600 image it's 8'h80, i want to change it to 4 for my system, because I want to read 4 columns in a go. But the thing is when I change them to any other values the image which i get on vga display is garbage. Also I have studied the complete Verilog code and functioning of this SDRAM, these burst lengths should be programmable I expect based on the code. can anyone please tell me how are these values fixed (8'h50 for 640x480 and 8'h80 for 800x600 image)?  



Just for reference, here are the projects which use camera and SDRAM controller whose code I borrowed: 

1) (

2) (


Thank you, 








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Honored Contributor I

did you find a solution to this at the end?