Test 2GB SODIMM with HPCII example driver

[Altera_Forum]

I have just brought up my SO-DIMM on Arria II GX using the DDR2 HPCII controller and the Altera-generated HPC1_example_driver Verilog. I'm suspecting that only a fraction of the complete memory is tested because 'test_complete' is asserted several times per second. This seems to quick for an exhaustive test of the whole memory space. 

 Can anyone give me some hints how to configure the example_driver to test the complete 2GB address space? I need this to verify that all address bits are correctly hooked up.  Is it sufficient to modify the MAX_ROW, MAX_BANK and MAX_COL definitions (see below)?  Thanks.  --------------------------------------------------------------------------------------------- ■ Sequential addressing writes and reads The state machine writes pseudo-random data generated by a linear feedback shift register (LFSR) to a set of incrementing row, bank, and column addresses. The state machine then resets the LFSR, reads back the same set of addresses, and compares the data it receives against the expected data. You can adjust the length and pattern of the bursts that are written by changing the MAX_ROW, MAX_BANK, and MAX_COL constants in the example driver source code, and the entire memory space can be tested by adjusting these values. You can skip this test by setting the test_seq_addr_on signal to logic zero.

[Altera_Forum]

hi man........ 

 i had a arria 2 gx with 1GB ddr2sodimm but i never use it......   had a example with ddr2sodim at altera wiki or altera forum i guess....     you can use your drive end custumize it for your memory    at sopc builder enter in your ddr2sodim drive ...select you memory and click modify parameters .......   and enter with your memory parameters......you can find it at your board user manual............save and recompile.....     i think if you changing MAX_ROW, MAX_BANK and MAX_COL can help....     cheers      Franz Wagner

[Altera_Forum]

Thanks. I'm however not using SOPC Builder. 

 I did tweak MAX_ROW, MAX_BANK and MAX_COL in my QII project and the whole test now takes about a second to run which seems reasonable. I will play around with signaltap to see whether the local interface address actually tests all addresses in my DDR2 SO-DIMM.

[Altera_Forum]

sounds good ...... 

 post results..... good luck   Franz Wagner