The end of AHDL?

[Altera_Forum]

Hello, was wondering what people thought about Altera's decision to remove the simulator within Quartus in version 10.0? Does this mean that AHDL will eventually die? I don't know of any other simulators that support AHDL, are there any? 

 Thanks, joe

[Altera_Forum]

Altera has released Quartus V9.1 this weekend, where do you get informations about quartus 10.0 ??? 

and why do you think AHDL dies if the simulator (ModelSim?) is removed ?

[Altera_Forum]

Future versions of Quartus II will not support a simulator. You will need to use ModelSim. Version 9.1 will be the last version to include a simulator. Hello ModelSim and testbenches! 

------ In the Quartus II software version 10.0 and onwards, the Quartus II simulator and Waveform Editor is removed. Therefore, you can run your simulation in the EDA simulators. The following EDA simulators are supported in the Quartus II software:  │ ModelSim │ ModelSim SE │ ModelSim Altera Edition (AE) │ ModelSim Altera Starter Edition (ASE) │ VCS/VCS-MX │ NCSim │ Active-HDL │ Riviera-PRO   http://www.altera.com/literature/hb/qts/qts_qii53017.pdf?gsa_pos=1&wt.oss_r=1&wt.oss=simulation%20quartus%20ii%20handbook&gsa_pos=5&wt.oss_r=1&wt.oss=altera%20simulator%20removed%20from%20quartus

[Altera_Forum]

I haven't given AHDL a thought in almost 10 years and wouldn't have noticed the removal of the simulator in Q10.0 as I haven't used that for almost as long. 

I think Altera are doing the right thing in concentrating their efforts on improving Quartus as a synthsiser and fitter rather than competing with modelsim and other simulators, especially as they give away a version of modelsim with Quartus.

[Altera_Forum]

Do you use Block Design Files (.bdf) in your projects? Since .bdf files must follow the AHDL bus naming conventions I wonder if they will stop supporting .bdf files soon. I always use .bdf files in my design it makes managing large projects much easier and easier to explain to others the design. 

 I saw the coming end to AHDL a while back and started moving to SystemVerilog.  Thanks, joe

[Altera_Forum]

No, just VHDL which is probably why I haven't had to deal with it. While I don't use graphical entry I can see the value of it and I'd have thought that would be worth supporting when the simulator isn't.

[Altera_Forum]

Im pretty sure they will continue supporting AHDL, just with the removal of the Quartus simulator (much reduced in functionality compared to modelsim) you will no longer be able to simulate raw code - you will have to simulate netlists which is slow and not what you want to do if you're trying to test functionality rather than timing.  

 AHDL isnt much more than a netlist language anyway, and being proprietry, Im glad this will hopefully put people off using it and using much better languages (VHDL or Verilog) instead. In addition, graphical entry can be useful, but again you're constrained by its limitations.