The issue encountered during testing after programming the R-tile PCIe DMA Design Example on the Agi

[xingyunzhidi]

I followed the instructions in section 3.5 of the Multi Channel DMA Intel® FPGA IP for PCI Express* Design Example User Guide for configuration, but encountered issues during testing. Below are the configuration details and the test result image.

[ventt]

Hi @xingyunzhidi,

Thanks for reaching out.

I want to replicate it on my end. Please share the following items:

1. The .ip file that you used to generate the R-Tile MCDMA Design Example.

2. Quartus version used.

Thanks.

Best Regards,

Ven

[xingyunzhidi]

Hello, my issue has been resolved, and I can now perform the DMA test normally. However, I’m a bit confused by the results. When testing with small data sizes (a few tens of KB), the measured bandwidth is less than 1GB/s. I also noticed that the test results in the Design Example User Guide are similar. What could be causing this? Also, is it possible to change the Qdepth value? If so, how can I modify it? Thanks!

[ventt]

Hi @xingyunzhidi,

Thanks for your updates.

Could you please share and confirm with us the following items:

1. The .ip file that you used to generate the R-Tile MCDMA Design Example.

2. Quartus version used.

This will help me understand the IP configuration, design example variant, and application run.

Thanks.

Best Regards,

Ven

[ventt]

Hi @xingyunzhidi,

Good day.

Could you please get back to us on the previous message?

Thanks.

Best Regards,

Ven

[ventt]

Hi @xingyunzhidi,

We have not received a response from you regarding our previous reply. Please log in to ‘https://supporttickets.intel.com’, view details of the desired request, and post a feed/response within the next 15 days to allow me to continue to support you.

After 15 days, this thread will be transitioned to community support.

Community users will be able to assist you with your follow-up questions.

Thanks.

Best Regards,

Ven