Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
21615 Discussions

The problem is a high level on the pins when the FPGA is turned on ep1с3т100с8n

Altera_Forum
Honored Contributor II
‎08-02-2017 07:03 AM
1,073 Views

Good day. 

In the finished product, which has been produced for a long time, they found a problem when supplying power to cyclone ep1с3т100с8n at the outputs a short high level of 3.3 V, even before the configuration was started. Is this normal and something can be done about it? Thank you.
0 Kudos

Link Copied

1 Reply
Altera_Forum
Honored Contributor II
‎08-02-2017 11:24 AM
499 Views

Before user configuration becomes effective, all IOs are pulled up by a weak pull-up resistor, a well documented behavior of all Altera FPGAs. 

 

The best solution is to chose active low level for critical signals, e.g. when turning on external devices. The next best is to add external pull-down resistors to these pins that override the weak pull-up.
0 Kudos
Copy link
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.