Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
The Intel sign-in experience has changed to support enhanced security controls. If you sign in, click here for more information.
19974 Discussions

The problem is a high level on the pins when the FPGA is turned on ep1с3т100с8n

Honored Contributor II

Good day. 

In the finished product, which has been produced for a long time, they found a problem when supplying power to cyclone ep1с3т100с8n at the outputs a short high level of 3.3 V, even before the configuration was started. Is this normal and something can be done about it? Thank you.
0 Kudos
1 Reply
Honored Contributor II

Before user configuration becomes effective, all IOs are pulled up by a weak pull-up resistor, a well documented behavior of all Altera FPGAs. 


The best solution is to chose active low level for critical signals, e.g. when turning on external devices. The next best is to add external pull-down resistors to these pins that override the weak pull-up.