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EBoln
New Contributor I
413 Views

The problem with two external PLL for LVDS RX

I have two identical interfaces:

Deserialization factor: 8

Channels: 8

Clock: 50MHz

 

If I implement only one interface, then everything is fine. However, after adding the second implementation, I get the following errors in Fitter stage:

 

Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 PLL output counter(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. Error (175020): The Fitter cannot place logic PLL output counter that is part of PLL Intel FPGA IP LVDS_PLL in region (0, 0) to (0, 8), to which it is constrained, because there are no valid locations in the region for logic of this type. Info (14596): Information about the failing component(s): Info (175028): The PLL output counter name(s): LVDS_PLL:i_LVDS1_PLL|LVDS_PLL_0002:lvds_pll_inst|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|counter[0].output_counter Info (175013): The PLL output counter is constrained to the region (0, 0) to (0, 8) due to related logic Error (16234): No legal location could be found out of 9 considered location(s). Reasons why each location could not be used are summarized below: Error (177013): Cannot route from the PLL output counter output to destination PLL LVDS output because the destination is in the wrong region Info (175027): Destination: PLL LVDS output cyclonev_pll_lvds_output_inst0 Info (175013): The PLL LVDS output is constrained to the region (89, 1) to (89, 75) due to related logic Info (175015): The I/O pad LVDS1_DATA[3] is constrained to the location PIN_Y25 due to: User Location Constraints (PIN_Y25) Info (14709): The constrained I/O pad is driven by this PLL LVDS output Error (11179): The PLL output counter could not be placed in any location to satisfy its connectivity requirements Error (11179): The PLL LVDS output could not be placed in any location to satisfy its connectivity requirements Info (175029): 9 locations affected Info (175029): PLLOUTPUTCOUNTER_X0_Y0_N1 Info (175029): PLLOUTPUTCOUNTER_X0_Y1_N1 Info (175029): PLLOUTPUTCOUNTER_X0_Y2_N1 Info (175029): PLLOUTPUTCOUNTER_X0_Y3_N1 Info (175029): PLLOUTPUTCOUNTER_X0_Y4_N1 Info (175029): PLLOUTPUTCOUNTER_X0_Y5_N1 Info (175029): PLLOUTPUTCOUNTER_X0_Y6_N1 Info (175029): PLLOUTPUTCOUNTER_X0_Y7_N1 Info (175029): PLLOUTPUTCOUNTER_X0_Y8_N1

 

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3 Replies
YuanLi_S_Intel
Employee
190 Views

Hi Evgeniy,

 

Before this, may i know which device you are using for this?

 

Thank You.

EBoln
New Contributor I
190 Views

BJona
Novice
190 Views

you can only have one PLL for one bank.

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