The voltage of I/O port from which a high frequency signal output

[Altera_Forum]

Hi, everyone! 

I'm a beginner in the Altera FPGA. Recently, I tried to use the output port of Cyclone 2C5 as the input clock of ADS830E (60MHz ADC). But I found when the output clock of FPGA reaches 8MHz, the output Vpp of FPGA is too low (the low level is 1V and the high level is 1.8V) for the ADC clock.   Is there any settings of quartus or other methods to deal with the problem?  Thanks for any hints.

[Altera_Forum]

Have you selected the 3.3 V LVTTL I/O standard at pin assignments for all of your pins? This can be done easily with pin planner. 

It is the ADC VDRV pin connected to the 3.3 v source?