I have 4 signals (analog) from DC-DC Buck Converter. FPGA is supposed to generate pwm signal out. But the weird thing is that. If 2 of signals from analog come the same time, then break pwm output. If there are not a the same time, then it's ok.
I have all modules run independent each other....
wire wEnable;
Filter FilterEnable (.clk(c0_100Mhz), .iSignal(iEnable), .oSignal(wEnable));
wire wfRef, wRef;
Filter FilterRef (.clk(c0_100Mhz), .iSignal(iRef), .oSignal(wfRef));
createRef createRef (.clk(c0_100Mhz), .iRef(wfRef), .iSync(wiSync1), .out(wRef));
// ------ Group 1 -----
wire wSync1, wPwm1, wiSync1;
Filter FilterSync_1 (.clk(c0_100Mhz), .iSignal(iSync[0]), .oSignal(wiSync1));
sync2pulse neg2pulse_1 (.clk(c0_100Mhz), .in(wiSync1), .out(wSync1));
SyncPwm PWM_1 (.clk(c0_100Mhz), .iEnable(wEnable), .iRef(wRef), .iSync(wSync1), .oPwm(wPwm1));
pwm2pulse pos2pulse_1 (.clk(c0_100Mhz), .in(wPwm1), .out(oPwmH[0]));
// ------ Group 2 -----
wire wSync2, wPwm2, wiSync2;
Filter FilterSync_2 (.clk(c0_100Mhz), .iSignal(iSync[1]), .oSignal(wiSync2));
sync2pulse neg2pulse_2 (.clk(c0_100Mhz), .in(wiSync2), .out(wSync2));
SyncPwm PWM_2 (.clk(c0_100Mhz), .iEnable(wEnable), .iRef(wRef), .iSync(wSync2), .oPwm(wPwm2));
pwm2pulse pos2pulse_2 (.clk(c0_100Mhz), .in(wPwm2), .out(oPwmH[1]));
Best,
Sean
