TimeQuest Ignoring create_generated_clock for SPI Clock Derived from Gated Divide-by-4 Signal (sck_r

[Sameer-sahu]

Hi all,

I'm encountering a persistent issue with Quartus Prime and TimeQuest Timing Analyzer where my create_generated_clock constraint is being ignored, even though I'm defining it on a clean, registered divide-by-4 clock signal used as the SPI clock in my design.

Design Setup

• FPGA family: [insert device/family here]

• Clocking:

  • PLL takes a 24 MHz input (clock_osc) and generates a 125 MHz clock (clk)

  • clk is used inside a module (tla2518) to derive a SPI clock

SPI Clock Implementation (tla2518 Module)

Inside tla2518, I create a divide-by-4 SPI clock from the 125 MHz clock:

reg [1:0] clk_div;
reg sck_raw;

always @(posedge clk or posedge reset) begin
if (reset) begin
clk_div <= 0;
sck_raw <= 0;
end else begin
clk_div <= clk_div + 1;
sck_raw <= clk_div[1];
end
end
This sck_raw signal is then passed to the top module via sck, and the final SPI output clock is generated as:
assign sck_o = (count < active) ? sck : 1'b0;
The goal is to constrain sdi (MISO from the ADC) based on the falling edge of sck_o, which is a gated version of sck.

# Base input clock (PLL input)
create_clock -name clock_osc -period 41.667 [get_ports clock_osc]

# PLL output clock (125 MHz)
create_clock -name clk -period 8.0 [get_pins {Top_TLA2518|pll_1|outclk_0}]

# Generated clock from internal divide-by-4 register
create_generated_clock -name sck -source clk -divide_by 4 Top_TLA2518|tla2518_inst_0|sck

# Propagate to output SPI clock
create_generated_clock -name sck -source Top_TLA2518|tla2518_inst_0|sck [get_ports sck_o]

# SPI input constraint (ADC → FPGA)
set_input_delay -clock sck -clock_fall -max 16.0 [get_ports sdi]
set_input_delay -clock sck -clock_fall -min 0.0 [get_ports sdi]

Despite the clean divider and structurally correct constraints:

• TimeQuest ignores the create_generated_clock for sck

• The clock does not appear in report_clocks

• TimeQuest continues to treat sck or sck_raw as a base, unconstrained clock
  

My understanding is that because:

• sck_o is gated using (count < active)

• The SPI clock (sck_o) is not toggling continuously

• TimeQuest does not consider it a proper periodic clock

As a result, sck_raw and sck are not treated as valid generated clocks, and any constraints associated with them are ignored.

I want to:

• Apply timing constraints to sdi (ADC MISO), which is launched on falling edge of sck_o

• Have TimeQuest recognize the divide-by-4 SPI clock as a valid generated clock

  • Am I missing something in the create_generated_clock usage?

  • Is there a way to force TimeQuest to preserve the generated clock if it's used only for output?

  • Should I use a virtual clock instead as a reference for SPI timing?

  I’ve attached my .sdc and design excerpts if needed. Any insight or workaround would be highly appreciated.

  @
  
  

[sstrell]

The output of a PLL should be a generated clock, not create_clock.  Depending on your target device, you may need to include derive_pll_clocks to specify the output generated clocks from the PLL.  If it's Stratix 10 or Agilex, you don't have to issue this command and you should remove the constraint for outclk_0.  Does outclk_0 appear in report_clocks?

Since you are using a PLL anyway, why aren't you just generating sck from that instead of building a divider?

Your -source should point to the output pin of the PLL (get_pins) to guarantee the correct reference is used as the source.

Also, you named both generated clocks the same in your .sdc.  They can't both be sck.

[RichardTanSY_Altera]

Thank you sstrell for answering.

Hi OP,

Does sstrell's suggestion helps?

Do you have further inquiry?

Regards,

Richard Tan

[RichardTanSY_Altera]

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