TimeQuest report timing finds 2 paths inside the Cyclone 2 FPGA for the same design path

[Cliver1]

Hello, when I analyse the path from P1_EnergyMonAInClk40m[6] to P1_PeakPowerClk40m[6] for example in my design using Report Timing in TimeQuest 2 paths are reported with different timing delays. The attached timing report screenshots and chip planner show what is happening.

P1_EnergyMonAInClk40m[6] is clocked in from I/O pin AdcDa[6] on the rising edge of a 40MHz clock.

The device is a Cyclone 2 EP2C15AF256C8 and I use Quartus II 12 service pack 2 web edition.

Any ideas why the 2 paths are reported?

Thanks,

Clive

 

[Cliver1 · Accepted solution]

False alarm. There are 2 possible data paths in my design!

[SyafieqS]

Let me know if there is any other concern regarding this.

[SyafieqS]

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