TimeQuest with Stratix III to Stratix III I/F

[Altera_Forum]

I'm new to using TimeQuest and I can see how to constrain an interface to an external device with know clock to output, setup and hold time specifications. 

 I'm trying to send data serially between three Stratix III devices in series, the data originates in the first FPGA is transferred to the second where it is latched with an input register then at an output register and sent to the third FPGA. Basically with out known clock to output times for the FPGA's this seems like a moving target. If anyone has any insight into this I would appreciate any advice, the clock rate is 100MHz.   In a previous design with Stratix devices I phase shifted the clock +/- 90 degrees and re sampled the data prior to the output latch with one of the shifted clock and then sampled the clock on the receiving FPGA with the other shifted clock to improve setup and hold times. That may not be necessary with the Stratix III devices improved speed, but insight in how to specify that would be helpful as well.

[Altera_Forum]

How does your clock feed the three devices? Is it a board clock fanning out to all three, or running chip to chip with the data(source-synchronous)?  

Note that there is some "chicken and the egg" when it comes to I/O timing between FPGAs, since both devices have variance to meet timing. If timing is tight, you have to figure out what the best one side can do and then apply that to the other FPGA. If it's loose, just take your 10ns clock period, take out your board delay, and give half of that to each side to work with. If one doesn't make timing, start tweaking.

[Altera_Forum]

Thanks for taking a look at this. 

 In this case the clock fans out to the 3 FPGA's, I've started out using this scheme to transfer data between the boards but I also have the option of going source synchronous.    For now I would like to understand the basic approach with the clock fanned out to the three parts. I have been reading AN433 which appears to have some useful information even though it is written for source synchronous.   I've also noticed that the tco for the second FPGA are affected by meeting the setup and hold times for data from the first FPGA, much slower which in turn affects the timing in IC3. This makes me think I can't implement this without phase shifting the input and output clocks independently of the board clock and resyncing to the board clock in each device. Considering that source synchronous may be more desirable.

[Altera_Forum]

Fanning a single clock is easiest, but forces lower clock rates. Since you're registering your inputs and outputs(and most likely I/O registers get used, which will happen automatically due to your timing constraints), the output timing of an FPGA should not be affected by the input timing, or vice-versa. My feeling is that you should be able to do this without going source-synchronous, but I don't know all the details. (I would recomend using a PLL).