Timequest Report Metastability

[Altera_Forum]

Timequest seems to ignore all synchronization chains except those contained in a megafunction DCFIFO. For example with the following clock definitions: 

  create_clock -period "30.000 ns" -name {PCI_CLOCK} [get_ports {clk}] create_clock -period "10.172 ns" -name {PCLK1_PHY} [get_ports {F1_PCLK}]  set_clock_groups -asynchronous -group { PCI_CLOCK } -group {PCLK1_PHY}  instances of the code shown below do not show up in the Metastability Report. Does anyone know what might be causing this?  Thanks, Edwin.   module signal_sync(  input wire clk1,  input wire clk2,  input wire in,  output wire out,  input wire rst1,  input wire rst2 );  reg in_reg; reg [1:0] sync;   always @(posedge clk1 or posedge rst1) // Latch input begin  if (rst1)  in_reg <= 1'b0;  else  in_reg <= in; end  always @(posedge clk2 or posedge rst2) // Sync into the clk2 domain begin  if (rst2)  sync <= 2'b0;  else  sync <= {sync[0], in_reg}; end  assign out = sync[1]; // Generates the output pulse  endmodule   

[Altera_Forum]

If you go to Assignments -> Settings -> TimingQuest and set the metastability to Forced if Asynchronous, it will identify it. In general, this setting is too conservative for most designs, i.e. it will find asynchronous transfers where metastability is not a concern, and use them in its MTBF calculations. If that's the case, set this to Auto, so it will identify all asynchronous transfers but not do MTBF calculations. From that list you can force it on specific chains, i.e. do: 

set_instance_assignment -name SYNCHRONIZER_IDENTIFICATION "FORCED IF ASYNCHRONOUS" -to sync[0]  It will then identify that chain. (FIFOs have this built into them, since it's Altera's IP and they know it needs this analysis)

[Altera_Forum]

--- Quote Start ---  set_instance_assignment -name SYNCHRONIZER_IDENTIFICATION "FORCED IF ASYNCHRONOUS" -to sync[0]  --- Quote End ---   It would be better to add (embed) this assignment in the HDL source itself, like Altera does in it's own IP. So if you re-use your code (and re-usability is what we need my friend) this is executed automatically! For Vhdl see: http://quartushelp.altera.com/10.0/mergedprojects/hdl/vhdl/vhdl_file_dir_attribute.htm For Verilog see: http://quartushelp.altera.com/10.0/mergedprojects/hdl/vlog/vlog_file_dir_attribute.htm

[Altera_Forum]

Good point. If you pro-actively identify synchronization registers and have your own hierarchy that does it, then it's a great methodology. Of course the constraint has spaces in it, which makes the syntax a little questionable, but the following seems to work: 

(* altera_attribute = "-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS" *) reg [1:0] sync;

[Altera_Forum]

Thanks fellows for your expert help. 

Edwin.