Timing analysis error: Modelsim error vsim-3039

[Altera_Forum]

I have an 8b counter for learning timing analysis. I have completed Fitter, Assember, Timequest and EDA Netlist without any error. I have added the sdc file to the Assignment. When I run the gate level simulation in Modelsim, I get a notification that "PE Student edition supports only a single HDL". I think I am doing something wrong; I am attaching the transcript. Can someone help? 

thanks

[Altera_Forum]

The error message imply that there are mixed HDL languages in the design files. You will need Modelsim SE to support mixed HDL.

[Altera_Forum]

Thank you for the feedback. My code is strictly VHDL. Does it mean that I have some Verilog code there? I am attaching the code. Can you help me understand what is mixed here?

[Altera_Forum]

The timing netlist will be output from the compiler. And is probably in a different language to the test bench. Hence the problem. 

 Honestly - if you did good design practice and it meets your timing requirements, its probably quicker just to load the design on the chip and see if it works than run a timing simulation (11 years in the industry - ive never had to run a single timing simulation)

[Altera_Forum]

I notice from the code, the Q output has an asynchronous enable - you're better off without this - just stick the Q assignment outside the process.